Author Topic: How do I implement ESD protection for a voltage reference?  (Read 587 times)

0 Members and 1 Guest are viewing this topic.

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
How do I implement ESD protection for a voltage reference?
« on: August 09, 2018, 01:13:19 pm »
I knew something about electronics thirty years ago, but I've forgotten everything I once knew.  Re-learning at my age is going slow.  I may have some of the terminology wrong, or even be misunderstanding something basic.  Everything below is on an "as I understand it" basis.

I'm going to build some sort of semi-precision voltage reference that I'll have to carry around and find someone or someplace to measure the voltage precisely.  I'd like as robust ESD protection as possible but am not sure how to go about it.

It will quite likely use an op amp to butter the output.  In a Metrology thread ( https://www.eevblog.com/forum/metrology/best-way-to-protect-my-voltage-reference/msg1667924/?topicseen#msg1667924 ) about ESD protection for a voltage reference David Hess replied, in part:

You protect an output the same way that you protect an input.  Add series impedance to limit the current and shunt protection.

[snip]

For protection against ESD, a shunt capacitor and shunt diodes may be sufficient.

Any resistance in the series impedance would introduce an error of about a microvolt per ohm for a voltmeter with a 1 megohm input impedance if my math is correct.

I figured, and Mr. Hess seems to be saying, that shunt protection (capacitors, zener diodes, transient voltage suppressors) with no series impedance is better than nothing and might protect a device from a low energy ESD event.  Any series impedance you can fit in within your error budget would would be even better.

Am I understanding this correctly?

And finally my question.  Would an inductor in the series impedance help?  A ferrite bead or two, a larger inductor?  Inductors resist current change, ESD events seem to have a fast rise time which an inductor might slow down, maybe.  I can find a lot about driving capacitive loads with an op amp, but little about driving inductive loads.

Brak
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #1 on: August 09, 2018, 01:44:42 pm »
Series resistance seems paradoxical, no?



You do it like this -- inside the feedback loop. ;)

Ferrite beads aren't much impedance compared to ESD, and saturate quickly besides, but yes, that's a help, especially around bipolar circuits like TL431s (if that's the sort of thing you were thinking).  Chokes work best with caps -- don't exceed the C-load limit of the amp, or, more generally, avoid the region of instability for the device (e.g., TL431 is okay for C < 10nF or whatever, and >4uF or whatever).

The above circuit also works well for dealing with C-load while keeping the active device happy: note the out-to-in cap. :)

Also also, note that TL431 is basically an opamp with a horrendous (but suspiciously stable) input offset voltage, unidirectional output (it can only pull down, not push up), and +in tied to GND internally as it were.  Other refs vary (the LM4040 series is similar, but "PNP", i.e., referenced to the more-positive voltage node, AFAIK; a lot of fancier (REFxxx, AD, LT) parts have sense inputs that basically generalize this even further), but the same method applies. :)

Tim
« Last Edit: August 09, 2018, 01:49:51 pm by T3sl4co1l »
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #2 on: August 09, 2018, 02:37:29 pm »
Series resistance seems paradoxical, no?

Paradoxical, yes.

I think "inside the feedback loop" is what I was looking for.  I don't really understand the schematic you provided, it's been a long time.  But given the hint I should be able figure it out.

I haven't decided what to use.  I've got some new LM4040, other than that it's 25 year old stuff.  ICL8069, REF02, 1N829A.  And some OP177 op amps which might be suitable.  I'm thinking an "Old fashioned zener 10V reference".  https://www.eevblog.com/forum/metrology/old-fashioned-zener-10v-reference/

Thank you for your help.

Brak
 

Offline Andreas

  • Super Contributor
  • ***
  • Posts: 2016
  • Country: de
Re: How do I implement ESD protection for a voltage reference?
« Reply #3 on: August 09, 2018, 03:23:54 pm »
The above circuit also works well for dealing with C-load

Against ESD you could have a (low inductive) capacitor (>= 10 nF) at the output.
This gives a capacitive voltage divider with the ESD capacitance (typically 150 pF).

of course you can also put a varistor or transient zener parallel to the output.

with best regards

Andreas
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #4 on: August 09, 2018, 09:33:54 pm »
Just out of frame, actually, there are clamp diodes -- another good way to deal with that. :)  Or a zener/TVS.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #5 on: August 10, 2018, 02:24:22 pm »
The above circuit also works well for dealing with C-load

Against ESD you could have a (low inductive) capacitor (>= 10 nF) at the output.
This gives a capacitive voltage divider with the ESD capacitance (typically 150 pF).

of course you can also put a varistor or transient zener parallel to the output.

Yes, thank you.

I think I've got the shunt protection figured out.  I've got suitable capacitors of various values, nominal 15V TVSs, 12V 5W zeners.

It's getting the series impedance "inside the loop" that's puzzling me.  I may be getting too old for this.

Brak
 

Online David Hess

  • Super Contributor
  • ***
  • Posts: 7104
  • Country: us
  • DavidH
Re: How do I implement ESD protection for a voltage reference?
« Reply #6 on: August 10, 2018, 03:03:17 pm »
It's getting the series impedance "inside the loop" that's puzzling me.  I may be getting too old for this.

T3sl4co1l's schematic shows exactly how to place the series resistance "inside the loop".  Of course now you have two pins to protect from ESD, the output and inverting input.  The shunt protection diodes in this case are part of the operational amplifier and not shown.

Series resistors for ESD protection should really be high voltage "fusible" film resistors but in practice designers rarely bother.  In the past they used carbon composition resistors for this.

An inductor or ferrite bead in series with the output may still be useful as part of a decoupling circuit to keep RF out.  I would use a decoupling capacitor from the output to ground but doing so also means that the feedback capacitor becomes important to maintain stability of the feedback loop.  The circuit shown with an output capacitor to ground is pretty common for fault protected outputs.
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #7 on: August 11, 2018, 12:56:58 pm »
The shunt protection diodes in this case are part of the operational amplifier and not shown.

That's good to know.

One great thing that's changed in the last twenty-five years is the easy availability of datasheets.  Looking at OPA2171 "Figure 40. Equivalent
Internal ESD Circuitry Relative to a Typical Circuit Application" right now.

I'll figure it out.

Thanks,

Brak
 

Online David Hess

  • Super Contributor
  • ***
  • Posts: 7104
  • Country: us
  • DavidH
Re: How do I implement ESD protection for a voltage reference?
« Reply #8 on: August 12, 2018, 02:19:53 am »
Parts which are specifically designed to handle ESD and RF are more common now and it is nice that they document them because these features can cause problems in some circuits.

The OPA2171 looks pretty nice.  It is not quite a precision operational amplifier which would have less low frequency noise (0.1 to 10 Hz) but it is better than most general purpose parts (and better than needed to buffer an LM4040, see below):

LM4040 >20uVpp (Estimated, 2.5 volt, Proportionally higher for higher output voltages)
OPA2171 3.0uVpp
LT1008/LT1012/LT1097 0.50uVpp <- Lowest Input Bias Current Bipolar
OP07 0.35uVpp <- Inexpensive
LT1001 0.30uVpp
OP177 0.22uVpp (Calculated)
LT1007 0.06uVpp

The noise will only matter if your reference is quieter than your buffer which is unlikely.  An LM4040 has at least an order of magnitude more noise than even the OPA2171.  Your OP177s would be a fine choice if you want to use what you have but use them with external ESD protection diodes.
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #9 on: August 12, 2018, 03:00:58 pm »
I knew about the better protection built into newer ICs, I'd just never met it in person so to speak.  I was looking at the OPA2171 datasheet to familiarize myself with it.

I did get a few OP07 when I got the LM4040, 5V & 10V.  They looked good and _were_ inexpensive.

I just need to set aside some time to concentrate on this for a bit.

I read through the enormous LTZ1000 and LM399 threads a while back and don't remember much about any kind of output protection for the references.  Would anyone know offhand if there are any examples of such protection on the EEVblog?

Thanks again,

Brak

 

Offline Andreas

  • Super Contributor
  • ***
  • Posts: 2016
  • Country: de
Re: How do I implement ESD protection for a voltage reference?
« Reply #10 on: August 12, 2018, 03:47:36 pm »
Hello,

it all depends on where your reference has to go and withstand which levels.
At home you can use a ESD wrist strap and be fine.
But even there I use a 100nF WIMA at the output buffer (mainly against EMI but it also helps against ESD).

If your reference has to travel you may have to use further measures.
(at least the first travel standard of cellularmitosis seems to have a damage perhaps by ESD).
For my travel standard I use a PI-Filter to further reduce influence.
https://www.eevblog.com/forum/metrology/ad587lw-10v-precision-travel-standard/msg1449492/#msg1449492

If your device also has to withstand mis-use then have a look at the Fluke 732 cirquit diagram.
(additional gas discharge tube + transient zener).

with best regards

Andreas
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #11 on: August 12, 2018, 07:06:03 pm »
I intend to carry it somewhere to get someone to measure it accurately

I remembered what a pi filter was, so I recognized that.  My original question was about using an inductor for protection.

WIMA?  Would that be the metallized or foil/film, polyester or polypropylene, or does it matter?

Brak
 

Offline Andreas

  • Super Contributor
  • ***
  • Posts: 2016
  • Country: de
Re: How do I implement ESD protection for a voltage reference?
« Reply #12 on: August 12, 2018, 10:54:26 pm »
The exact type does not matter: but it should be a low inductance capacitor.
I use type MKS2

with best regards

Andreas
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #13 on: August 12, 2018, 11:58:09 pm »
Can't beat an SMT ceramic chip, it has no lead length.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 

Online imo

  • Frequent Contributor
  • **
  • Posts: 356
  • Country: 00
Re: How do I implement ESD protection for a voltage reference?
« Reply #14 on: August 13, 2018, 01:09:20 am »
Are there any rules how to set the capacity of the Wima cap for the ESD protection?
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #15 on: August 13, 2018, 12:28:05 pm »
I'm not real sure about this.  Especially not sure about the component values.

Does this look like something that might work with the right components?



Brak
« Last Edit: August 13, 2018, 12:35:38 pm by Brak »
 

Online David Hess

  • Super Contributor
  • ***
  • Posts: 7104
  • Country: us
  • DavidH
Re: How do I implement ESD protection for a voltage reference?
« Reply #16 on: August 13, 2018, 12:47:55 pm »
That looks about right.  That configuration is commonly used to drive capacitive loads and if you want the math, this application note from Analog Devices covers it under "In-loop compensation".

http://www.analog.com/en/analog-dialogue/articles/ask-the-applications-engineer-25.html

One such application involves the buffering or inverting of a reference voltage, driving a large decoupling capacitor. Here, CL is a fixed value, allowing accurate cancellation of pole/zero combinations. The low dc output impedance and low noise of this method (compared to the previous two) can be very beneficial. Furthermore, the large amount of capacitance likely to decouple a reference voltage (often many microfarads) is impractical to compensate by any other method.

With some care, you can also place a relatively large output capacitance (10 to 100 microfarad aluminum electrolytic or solid tantalum capacitor can work) directly from the operational amplifiers output to ground forcing "dominant pole" frequency compensation but I do not really recommend this unless you want to delve into the details of frequency compensation.  Some newer operational amplifiers can operate this way without restrictions; there is a list at the link.

 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #17 on: August 13, 2018, 01:05:58 pm »
Yeah, like that. Don't need D1-D3, since D4 is fine in a single-supply situation.  (Otherwise, clamp diodes to the supplies, or a bidirectional TVS or back-to-back zeners, would do.)

May want more supply, since 13 - 10 = 3V (if it were a RRO amp) isn't much current through the 100 ohm resistor.  Well, maybe not that bad, but YMMV.  Something to keep in mind.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #18 on: August 13, 2018, 01:47:12 pm »
Excellent, thank you both.  That gives me something concrete to study on.

I had the analog link bookmarked.

Does the "Seven Transistor Labs" have anything to do with "Six Transistor Radios"?  I still remember my first one.  It was red and so small it'd fit in my Dad's shirt pocket.  IIRC one of the transistors was used as a diode, but they could advertise six transistors.

Brak

 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #19 on: August 14, 2018, 04:59:36 am »
Nah, more that I like to make circuits like this from time to time,



which, if you ignore the complementary emitter follower, and count the TL431 as a single transistor, almost works... :P

(This circuit has functionality similar to UC3842, but with far fewer transistors, hence the challenge.  Doing it in less than ~4 is iffy, and you're giving up things like input voltage range, or output overload handling, when you do that.)

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 

Offline Brak

  • Contributor
  • Posts: 13
  • Country: us
Re: How do I implement ESD protection for a voltage reference?
« Reply #20 on: August 14, 2018, 12:52:18 pm »
Are there any rules how to set the capacity of the Wima cap for the ESD protection?

I'm certainly no expert, don't take my advice.

I've always assumed, without really thinking about it, the larger the capacitance the better within whatever limits the reference will drive.  And that several capacitors of different values and perhaps different technologies, having different resonant frequencies, would be better than a single capacitor.  I guess I'm assuming this counts as a bypass capacitor.

Our host has a YouTube video, "Bypass Capacitor Tutorial" at:

 

I think Dave says towards the end of the video that it's really hard to be sure what's happening without a lot of expensive equipment.

Brak
« Last Edit: August 14, 2018, 12:54:00 pm by Brak »
 

Offline Andreas

  • Super Contributor
  • ***
  • Posts: 2016
  • Country: de
Re: How do I implement ESD protection for a voltage reference?
« Reply #21 on: August 14, 2018, 05:05:50 pm »
Hello,

the picture is only a theoretical one.
Practically (when using capacitors of the same type) the minimum ESR is lower with larger capacity value.
So the "advantage" of using a lower capacity value at higher frequencies is much smaller than in Daves diagram.

Especially when using a bypass capacitor and if you take in account that from capacitor to the chip of the integrated cirquit are at least 5 mm (0.2") lead length = inductor of 5 nH.
So if you look at the effective impedance which is seen from the chip it is all the same regardless of the capacitor above the self resonant frequencies.

With best regards

Andreas
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 10941
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: How do I implement ESD protection for a voltage reference?
« Reply #22 on: Yesterday at 01:36:47 am »
Dave misses the problem with paralleling capacitors: each time two curves cross, there is a peak where impedance goes up.  The amount it goes up by, is symmetrical with the amount it goes down by.  The centerline both amounts are relative to is the resonant impedance Zo = sqrt(L/C).  One resonance is series mode, with a minimum impedance of ESR, and a Q of Zo / ESR.  The other is parallel mode, with a maximum impedance of Zo * Q.

This is why it's more critical to have a well damped supply.

Tim
Seven Transistor Labs, LLC
Electronic Design, from Concept to Layout.
Need engineering assistance? Drop me a message!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf