How good is this crystal oscillator design?

[amin08]

I'm designing an Atmega328P-AU based WiFi development board for my school project, and as you know, crystal oscillators may take some effort to layout, especially when we have a WiFi module. Any advice or suggestion is appreciated!

[orolo]

I'm far from an expert in layout, but from your left cap to the right one there is a long, winding path around the crystal, enclosing a big area, so they hardly share a common ground. Maybe it would be better if you flipped both capacitors, taking the left trace out of the way, so their groundings are in close contact. Also, I don't know if this will decrease very much the parasitic capacitance, but you could leave a bit more clearance between the crystal pads and the ground plane; most probably this is not very important.

Edit: better yet, take a look at this app note. Flip and move up the left cap, making it jump over the right trace, placing both caps very near to MCU ground. Optimal.

[T3sl4co1l]

One tiny little sliver tying it to ground, no vias, no bottom side ground plane?

Layout around the crystal is highly overblown anyway.  If you don't have any way to measure a difference, then why bother doing a thing?

Tim

[amin08]

Just edited!
 Added ground plate 

[basinstreetdesign]

Orolo's comments still apply.  The cap connected to pin 8 of the MCU should be flipped to jump over the track to the other cap and make connection to ground near MCU's pin 5.

[orolo]

As basinstreetdesign said, you still have issues with the capacitor layout. Look, a digital clock is a square wave signal, which means that, if the clock speed is 16MHz, there will be components in that signal very faster than 16MHz, called harmonics. These can go well into the hundreds of MHz. At such high frequencies, a signal will take the path of least inductance, which means a path that circles the least possible area. If a fast signal is forced into a path with a big area, the signal will be either weakened or take another path and will arrive at a different time than other components. The result will be a distorted clock signal, or a non-working clock.

Now look at your capacitors. The clock is using a Pierce oscillator circuit, that requires that the two capacitors C1 and C2 share the same ground. In your circuit, the least area path from the ground in one capacitor to the other is painted yellow:



That is not good. A better idea would be to flip the Pin 8 capacitor, so both caps end very close together, and near the MCU ground pin 5 (sorry for the horrible graphic):



Now the path for the fast signals is much shorter, and the circuit will probably work better.

Then there are other details, that I think Tim hinted at. Possibly, you should isolate pins 5, 7 and 8 in a single patch on the upper plane, and connect with a single via to the ground plane, near pin 5. Or make a separate section of the ground plane only for the clock area, heavily conected by vias to the upper patch, and then connect the upper patch with only one connection to the MCU ground. Essentially, you don't want any AC signal entering or leaving the clock circuit, and the best way of making sure of that is isolating the whole clock section except for one connection for the DC ground bias. And probably, the whole clock section could be made smaller than what you have now, and with more symmetrical connections to each clock pin. There are very gifted people here who will be able to fill the details better than me.

[T3sl4co1l]

As basinstreetdesign said, you still have issues with the capacitor layout.

Well, "issue" is rather strong here...

Then there are other details, that I think Tim hinted at. Possibly, you should isolate pins 5, 7 and 8 in a single patch on the upper plane, and connect with a single via to the ground plane, near pin 5. Or make a separate section of the ground plane only for the clock area, heavily conected by vias to the upper patch, and then connect the upper patch with only one connection to the MCU ground. Essentially, you don't want any AC signal entering or leaving the clock circuit, and the best way of making sure of that is isolating the whole clock section except for one connection for the DC ground bias. And probably, the whole clock section could be made smaller than what you have now, and with more symmetrical connections to each clock pin. There are very gifted people here who will be able to fill the details better than me.

I certainly wouldn't go so far as to do that, but more to the point, I shall reiterate: if you can't measure it, it doesn't matter.

It seems unlikely the OP, a beginner, will be involved in strong RF fields or high switching currents (a risk factor for upsetting a crystal oscillator), and only needs the crystal to start up and run at approximately a stable frequency.  If this were a timing critical application (like a timepiece, or precision instrument), a nicer crystal would be needed anyway, and it might be better to use a completely different approach (a silicon oscillator or TCXO?) instead of a crusty MCU oscillator.

For the general purpose use I assume the OP is after, the parts can be probably about anywhere on the board and it'll still work.  It might be rather susceptible if they're, like, opposite sides, but that'd be pretty obviously silly.

The cap move is good: even if it's not electrically necessary, it's good semantically.  That is, keep in mind the ground return paths between various components, and keep those paths short, just as you keep the signal traces short.   Then, add ground plane, and stitching vias.  Remember the negative space around signal traces -- that gets filled in with ground -- is also a signal path all its own, and traces cutting through it create slots and gaps that need to be filled in by connecting the top and bottom layers with vias on either side of traces.

Tim