How is the wide voltage range realized on a Saleae Logic Pro 16 logic analyzer?

[0x1af]

 Hello everyone!

First of all, I hope I picked the right subforum, I was not entirely sure.

I am interested to understand how the wide signal input range for logic analyzers like the Saleae Logic Pro 16 [1] or
DreamSourceLab DSLogic Plus [2] has been realized.

Does one of you know more about this?

Is the specified maximum frequency supported over the full input signal voltage range  on these devices?

I was thinking that the internal clamping diodes of the FPGA might be used, but I am not sure and so far I did not find further resources on this.
Could I find diodes with similar properties as external components?

The background is, I would like to build an addon-board (as open source)  for the FX2LP dev board (the one which is widely used as cheap logic analizer).
Once finished, I would want the addon board to support an extended input range with high impedance and provide input protection.

I have started looking at the SN74LVCH8T245 [3],  the 74HC4050 [4], and ESD Diodes in general,
but then I thought it might be good for me to gain a better understanding of already developed products first.

Thank you a lot!

[1] https://sigrok.org/wiki/Saleae_Logic_Pro_16
[2] https://sigrok.org/wiki/DreamSourceLab_DSLogic_Plus
[3] http://www.ti.com/lit/ds/symlink/sn74lvch8t245.pdf
[4] https://www.nxp.com/docs/en/data-sheet/74HC4050.pdf

[thm_w]

DSlogic was reportedly using this chip for ESD protection: https://www.onsemi.com/pub/Collateral/CM1213A-D.PDF
https://sigrok.org/wiki/DreamSourceLab_DSLogic

Newer models use a different chip but I can't quite make it out: https://www.eevblog.com/forum/testgear/upgrading-dslogic-basic-to-plus-without-eeprom-modification/msg2806408/#msg2806408
Anyway it will have similar purpose.

They specify input:
-0.6V — 6V
+/-30V with provided probe-wires
400MHz max sample rate.

You can see the probe cable circuit on the sigrok wiki you've linked has a 100k resistor which allows this higher input voltage.

The main issue they had was signal integrity with the cheap flying lead type probe wires, so they've changed it to micro-coax style cables.

[0x1af]

 thm_w, thank you for looking into this and your response  .

Newer models use a different chip but I can't quite make it out: https://www.eevblog.com/forum/testgear/upgrading-dslogic-basic-to-plus-without-eeprom-modification/msg2806408/#msg2806408
Anyway it will have similar purpose.

I took some time and searched for it.
The marking on the chips do look the same as under [1].
It seems to be "4D78t" for example (with the 78 written vertically).
I found the PRTR5V0U4D, which has the 4D marking code (see [2] datasheet).
To be sure,  I searched  for actual pictures of the PRTR5V0U4D and it appears to have this vertical text.

I am probably missing something, but that is where I am stuck right now  :
The Spartan FPGA chip has a recommended  range of -0.5 V - 4.0 V  (Input voltage relative to GND All I/O standards (except PCI) , page 3 [3]),
while the ESD diode array has a breakdown voltage VBR of somewhere 6 - 9 V ([2], page 4).
Also the probe wire circuit under [4] is not a voltage divider, so as I understand it, it would only limit the current?
Could it be that this chip is really just used for ESD protection and
something else (like other clamping diodes) are used to extend the voltage range?

Thank you!

[1] https://sigrok.org/wimg/3/38/Dslogic_plus_pcb_front.jpg
[2] https://assets.nexperia.com/documents/data-sheet/PRTR5V0U4D.pdf
[3] https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf
[4] https://sigrok.org/wiki/File:Dreamsourcelab_dslogic_plus_probe_circuit.png

[thm_w]

thm_w, thank you for looking into this and your response  .

Newer models use a different chip but I can't quite make it out: https://www.eevblog.com/forum/testgear/upgrading-dslogic-basic-to-plus-without-eeprom-modification/msg2806408/#msg2806408
Anyway it will have similar purpose.

I took some time and searched for it.
The marking on the chips do look the same as under [1].
It seems to be "4D78t" for example (with the 78 written vertically).
I found the PRTR5V0U4D, which has the 4D marking code (see [2] datasheet).
To be sure,  I searched  for actual pictures of the PRTR5V0U4D and it appears to have this vertical text.

I am probably missing something, but that is where I am stuck right now  :
The Spartan FPGA chip has a recommended  range of -0.5 V - 4.0 V  (Input voltage relative to GND All I/O standards (except PCI) , page 3 [3]),
while the ESD diode array has a breakdown voltage VBR of somewhere 6 - 9 V ([2], page 4).
Also the probe wire circuit under [4] is not a voltage divider, so as I understand it, it would only limit the current?
Could it be that this chip is really just used for ESD protection and
something else (like other clamping diodes) are used to extend the voltage range?

Thank you!

[1] https://sigrok.org/wimg/3/38/Dslogic_plus_pcb_front.jpg
[2] https://assets.nexperia.com/documents/data-sheet/PRTR5V0U4D.pdf
[3] https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf
[4] https://sigrok.org/wiki/File:Dreamsourcelab_dslogic_plus_probe_circuit.png

Good find on the ESD diode.

So the probe wire schematic is just the components on the probe itself. There are also resistors on the main board.
From what I see, there is one resistor on the input to ground (R63-66, etc.) and then one resistor in series with the FPGA (R30, 32, 34, 36, etc.).

The two resistors will form a divider (one in probe and one on board), reducing the input voltage slightly.
The series resistor on the board will limit current and smooth out the signal a bit for impedance matching.
They state input threshold is anywhere from 0.1 to 5V, I'm not exactly sure how that part is done, may be related to the buck converter near the USB.

I can trace out the circuit and measure the values of the resistors when I get a chance.

[thm_w]

The series resistor (R30, etc.) measures as 33 ohms.
The other resistor (R63, etc.) measures as 149kohm

So 60V in would produce ~36V across 149k. But it would be clipped by that ESD diode as soon as it goes above 6V.
You should see 0.5mA worst case current flow (60V - 6V / 100k). Dissipation of ~30mW, which is the rating of a 0402 resistor.

[0x1af]

thm_w, thank you once again  

I tried to put everything in a ltspice schematic. Does it look ok to you?
I have not yet found a spice model for the nexperia ESD diode array, but I will keep looking or maybe use a similar ESD diode from Ti.


The 100k + 149k + 500 and something would match nicely the impedance stated in the DSLogic datasheet  [1].

What I still do not understand, if the schematic is correct, the FPGA would still have to tolerate 6V on its input pins, while from what I have seen in the datasheet the maximum seems to be 4.45 V ([2], page 2).
Am I misreading the datasheet?






[1] https://www.dreamsourcelab.com/doc/DSLogic_Plus_Datasheet.pdf
[2] https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

[thm_w]

Looks good.
This spec is what we are interested in for the FPGA from PDF you linked:

Maximum current through pin using PCI I/O standard when forward biasing the clamp diode. = 10mA
Maximum current through pin when forward biasing the ground clamp diode. = 10mA

So the internal clamping diodes will handle ~10mA.
If we are using the supplied probes, its going to be OK, current will be limited to the previously mentioned ~0.5mA

Xilinx themselves will tell you not to do this of course: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Spartan-7-Clamp-Diode-Conducted-Voltage-and-Max-Current-Details/td-p/1042968
But its a low cost device, and many people have "abused" ESD clamp diodes in this way.


For direct input (-0.9 to 6V no probe) either we are operating beyond spec, or missing some details:
- 6V directly and assume FPGA is clamping at 5V (slightly above vccio), we get 30mA, above spec.
- D1 appears to be a TVS. but that doesn't areally help us as that is the 5V rail.
- If the ESD diodes were tied to a lower voltage (eg not 5V), then they would draw even more current.. not good.

[sslupsky]

Check the connection to VDDIO on the FPGA ... I suspect they change the VDDIO voltage which in turn changes the threshold voltage.  There maybe multiple VDDIO domains, I am not familiar with the particular FPGA here, so pay attention to the VDDIO pins near the IO used for the logic analyzer inputs.