All address lines, all chip selects, all control signals, connected together in common for all chips. All data lines arranged into 4 x parallel buses of 16 bits each, for a total of 64 bits per bus cycle. DDR2 uses SSTL2 signaling which requires controlled impedance traces, minimal stub lengths, matched trace lengths, series and/or stub terminator resistors, and requires low noise (typically all signals are routed over a common plane which is connected to VREF, along with the terminators and a VREF supply controller chip).
As far as I know, the 4 pages are combined transparently in the chip design, probably each page being accessed independently, then all four WORDs queued up for the data burst. The DDR2 controller or interface device should be aware of the configuration and transfer signals necessary to use these devices, on its own.
Tim