EEVblog Electronics Community Forum

Electronics => Beginners => Topic started by: Jane on June 10, 2015, 05:42:26 am

Title: How memory chips are connected
Post by: Jane on June 10, 2015, 05:42:26 am

In a  device there are 4 pcs of   ELPIDA EDE5116AJBG-LI (32M words × 16 bits) DDR2 SDRAM chip. According to  its datasheet, organization of that  DDR2 SDRAM chip should be 8M words × 16 bits × 4 banks
CPU, used in that device , uses 64-bit DDR2 interface  and the total RAM is 256MB.
How must be connected those 4 pcs of   ELPIDA EDE5116AJBG-LI chips to provide 256 MB RAM capacity?
Thanks

Title: Re: How memory chips are connected
Post by: slateraptor on June 10, 2015, 06:24:08 am

Are you trying to understand the arithmetic of how 4 of these memory devices make 256MB memory, or are you seriously expecting someone to draw you a schematic?

Title: Re: How memory chips are connected
Post by: John_ITIC on June 10, 2015, 07:04:43 am

Take a look at the various 64-bit wide SODIMM/DIMM specs. Vendor datasheets (Micron and others) also contain information how chips are connected on their DIMMs.

https://www.google.com/?gws_rd=ssl#q=sodimm+jedec+spec (https://www.google.com/?gws_rd=ssl#q=sodimm+jedec+spec)

Title: Re: How memory chips are connected
Post by: T3sl4co1l on June 10, 2015, 09:16:54 am

All address lines, all chip selects, all control signals, connected together in common for all chips.  All data lines arranged into 4 x parallel buses of 16 bits each, for a total of 64 bits per bus cycle.  DDR2 uses SSTL2 signaling which requires controlled impedance traces, minimal stub lengths, matched trace lengths, series and/or stub terminator resistors, and requires low noise (typically all signals are routed over a common plane which is connected to VREF, along with the terminators and a VREF supply controller chip).

As far as I know, the 4 pages are combined transparently in the chip design, probably each page being accessed independently, then all four WORDs queued up for the data burst.  The DDR2 controller or interface device should be aware of the configuration and transfer signals necessary to use these devices, on its own.

Tim

Title: Re: How memory chips are connected
Post by: Jane on June 10, 2015, 07:51:59 pm

Thank you for the replies.
And if DDR2 fails, is there any way how to find out which chip, of those 4 chips, is faulty?

Title: Re: How memory chips are connected
Post by: Len on June 10, 2015, 08:26:26 pm

Quote from: Jane on June 10, 2015, 07:51:59 pm

And if DDR2 fails, is there any way how to find out which chip, of those 4 chips, is faulty?

Sometimes the old finger test can tell you, as here:
https://youtu.be/UPSLgY_-4HE?t=20m33s

Title: Re: How memory chips are connected
Post by: amyk on June 10, 2015, 08:49:33 pm

https://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/DDR2/240-pin%20Unbuffered%20DIMMs (https://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/DDR2/240-pin%20Unbuffered%20DIMMs)

Schematics, BOM, and board layouts are there. Need to register but it's free. Look for JESD79-2 also, that's the main DDR2 standard.