Author Topic: How much noise on power rail is normal?  (Read 9813 times)

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Offline chicken

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How much noise on power rail is normal?
« on: July 11, 2014, 11:29:48 am »
I work on a project with an MCU and a radio receiver IC. It works well, but more range/sensitivity is always better B-)

The receiver IC claims sensitivity down to less than -100 dBm, but in my design packet integrity starts to drop off around -60 dBm. The radio reports an RSSI close to the absolute minimum (-120 dBm) when not connected to an antenna, jumping to -110 to -90 dBm depending on antenna. But I doubt this is reflective of the actual noise floor. The radio being a single IC makes it hard to diagnose that part in more detail.

Checking out the 3.3 V power rail I see about 10 mVpp of noise, with a prominent (IIRC mostly upward) bump at around 10 kHz. This probably correlates with the 9600 bps data clock waking up the MCU and toggling an indicator LED.

All capacitors recommended by the datasheets and app notes are in place. And with less than 30 mA drawn, the 150 mA LDO has plenty of headroom.

Is it worthwhile trying to squeeze out those 10 mV? I.e. will it make a difference?

If so, how? More capacitance? Separate power trace to the radio? Or even give the radio its own LDO? Or separated grounds that are joined near the LDO?
 

Offline m12lrpv

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Re: How much noise on power rail is normal?
« Reply #1 on: July 11, 2014, 12:39:03 pm »
Facing the similar issues myself with a project I'm working on and because of that I'm also very keen to get some tips on smoothing out the power rail.

Decoupling as per data sheets just never seems to work. Increasing the capacitance by a factor of 10 or more helps but never really resolves the issue.

 

Offline kizzap

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Re: How much noise on power rail is normal?
« Reply #2 on: July 11, 2014, 02:47:59 pm »
some sort of LPF would be useful. There are numerous ways to implement it too.

a common method is to have either a RC or LC LPF at the input to the device, bringing the -3dB point to somewhere well before the frequency you are concerned about. for example, if you make a LPF with the -3dB point at roughly 1kHz, iirc you should have a -20dB reduction in the peak of the 10kHz signal, or a ÷10 in peak value.

other methods have different pros/cons, and YMMV.

-kizzap
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Offline VK5RC

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Re: How much noise on power rail is normal?
« Reply #3 on: July 11, 2014, 02:56:43 pm »
I am not an expert in the area but digital and rf don't mix well,  the harmonics from a digital signal go a long way,  I would tend to have two power supplies,  regards Rob
PS also watch the 'ground'  as well.
« Last Edit: July 11, 2014, 02:58:57 pm by VK5RC »
Whoah! Watch where that landed we might need it later.
 

Offline Richard Crowley

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Re: How much noise on power rail is normal?
« Reply #4 on: July 11, 2014, 04:03:35 pm »
I work on a project with an MCU and a radio receiver IC. It works well, but more range/sensitivity is always better B-)

The receiver IC claims sensitivity down to less than -100 dBm, but in my design packet integrity starts to drop off around -60 dBm....
Checking out the 3.3 V power rail I see about 10 mVpp of noise, with a prominent (IIRC mostly upward) bump at around 10 kHz. This probably correlates with the 9600 bps data clock waking up the MCU and toggling an indicator LED.
Yeah, maybe.  It seems like it would be simple enough to do an experiment where you power the test circuit from a battery (with a few capacitors of various types and values  for good measure).

Quote
The radio reports an RSSI close to the absolute minimum (-120 dBm) when not connected to an antenna, jumping to -110 to -90 dBm depending on antenna. But I doubt this is reflective of the actual noise floor. The radio being a single IC makes it hard to diagnose that part in more detail.
What leads you to believe the noise is getting in through the power supply after that experiment? I would far more suspect it was simply getting in through the antenna. I would at least perform a test enclosing the receiver within a metalic shield with a proper coaxial antenna connection.
 

Offline AndyC_772

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Re: How much noise on power rail is normal?
« Reply #5 on: July 11, 2014, 04:32:59 pm »
It's impossible to advise on this problem without seeing the physical layout of your circuit. Can you post a photo showing exactly how it's constructed?
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #6 on: July 11, 2014, 07:26:58 pm »
some sort of LPF would be useful. There are numerous ways to implement it too.

a common method is to have either a RC or LC LPF at the input to the device, bringing the -3dB point to somewhere well before the frequency you are concerned about. for example, if you make a LPF with the -3dB point at roughly 1kHz, iirc you should have a -20dB reduction in the peak of the 10kHz signal, or a ÷10 in peak value.

RLC decoupling used to be common with a single layer inductor wound directly around a low value resistor which is needed to lower the Q.  This can be applied separately to different circuit blocks to prevent both incoming and outgoing noise.

Wideband decoupling requires low parasitic capacitance in the inductor and they make special ferrite beads for this that are incredibly effective.  At high frequencies just the circuit board trace acts as the inductor.

Ground and power loops need to be avoided.  If a ground plane is used, slots can be used to route digital return currents away from sensitive nodes.

A 10 millivolt change might just reflect the load regulation of the LDO when driving the LED.  Be careful about routing the power and ground currents for the LED through sensitive nodes.
 

Offline lgbeno

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Re: How much noise on power rail is normal?
« Reply #7 on: July 11, 2014, 11:04:37 pm »
Before you try to reduce the noise, maybe you want to wire in a external "cleaner" source directly from batteries or some linear ac supply
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #8 on: July 12, 2014, 02:08:07 am »
Before you try to reduce the noise, maybe you want to wire in a external "cleaner" source directly from batteries or some linear ac supply

He says it is already using a LDO regulator so I am not sure how much cleaner it can be.  I would assume most of the noise is coming from the microcontroller and associated digital circuitry.
 

Offline lgbeno

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Re: How much noise on power rail is normal?
« Reply #9 on: July 12, 2014, 02:16:30 am »

Before you try to reduce the noise, maybe you want to wire in a external "cleaner" source directly from batteries or some linear ac supply

He says it is already using a LDO regulator so I am not sure how much cleaner it can be.  I would assume most of the noise is coming from the microcontroller and associated digital circuitry.

Yeah seems like a very nebulous endeavor.

Also noise means a lot of things.  "Thermal noise", "noise" from digital circuits, etc etc.  it's difficulty to optimize and measure.  Just because there is 10mV of fuzz on a scope, how much is measurement uncertainty or attributed by the scope it's self.
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #10 on: July 12, 2014, 02:55:42 am »
Thank you all for chiming in, great suggestions!
 
First of all I apologize for not using the right terms. I'm clearly the n00b here. To clarify terms, I talk about 10mV ripple. The ripple looks roughly the same across the whole rail (close to LDO, close to MCU, close to radio) with a prominent bump roughly every 10ms. The rest is not perfect, but clearly less than 5mV.

Quote
Before you try to reduce the noise, maybe you want to wire in a external "cleaner" source directly from batteries or some linear ac supply

Great input. I will definitely try to use a battery to test if a clean supply actually makes a difference.

Quote
some sort of LPF would be useful. There are numerous ways to implement it too.

a common method is to have either a RC or LC LPF at the input to the device, bringing the -3dB point to somewhere well before the frequency you are concerned about. for example, if you make a LPF with the -3dB point at roughly 1kHz, iirc you should have a -20dB reduction in the peak of the 10kHz signal, or a ÷10 in peak value.
Quote
Wideband decoupling requires low parasitic capacitance in the inductor and they make special ferrite beads for this that are incredibly effective.  At high frequencies just the circuit board trace acts as the inductor.

LPF with LC or ferrite bead is something that I will try as well. But I wonder if ferrite beads are any good to filter this kind of ripple. The datasheets of the SMD beads I looked at all talk about 1MHz+.

Quote
I would at least perform a test enclosing the receiver within a metalic shield with a proper coaxial antenna connection.

I already covered the radio part of the PCB with an RF shield. In field tests it didn't seem to make much of a difference, but hard to tell without being able to measure the noise within the receiver circuit.

Quote
It's impossible to advise on this problem without seeing the physical layout of your circuit. Can you post a photo showing exactly how it's constructed?

See attachment. I highlighted the 3.3V power rail in red.

Quote
Quote
The radio reports an RSSI close to the absolute minimum (-120 dBm) when not connected to an antenna, jumping to -110 to -90 dBm depending on antenna.
What leads you to believe the noise is getting in through the power supply after that experiment?

I think this to be a red herring myself. The IC is tuned to the frequency of interest (~162MHz) so RSSI probably just measures the level of white noise. Transmission errors (CRC) start to get very frequent at RSSI levels 30dBm higher so I wonder if the power supply ripple disrupts the radio's decoding from GMSK to bitstream.

Thank you all again for chiming in. Really appreciated!
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #11 on: July 12, 2014, 03:16:36 am »
Quote
Wideband decoupling requires low parasitic capacitance in the inductor and they make special ferrite beads for this that are incredibly effective.  At high frequencies just the circuit board trace acts as the inductor.

LPF with LC or ferrite bead is something that I will try as well. But I wonder if ferrite beads are any good to filter this kind of ripple. The datasheets of the SMD beads I looked at all talk about 1MHz+.

They will not do anything for the low frequency ripple but often the problem is the high speed edges accompanying it.
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #12 on: July 12, 2014, 03:24:54 am »
Yeah seems like a very nebulous endeavor.

Also noise means a lot of things.  "Thermal noise", "noise" from digital circuits, etc etc.  it's difficulty to optimize and measure.  Just because there is 10mV of fuzz on a scope, how much is measurement uncertainty or attributed by the scope it's self.

The difficulty of probing and measurement is definitely not to be overlooked.  I have spent my own share of time tracking down phantom noise problems.

The two techniques I like to use are soldering a coaxial pigtail into the circuit to make a coaxial connection to the probe and of course differential probing.  The coaxial pigtail is very handy when leaking magnetic flux in a switching circuit would otherwise contaminate the signal via the relatively large loop area of a traditional probe and ground lead.  Low power supply impedances make the added capacitance of the pigtail insignificant.

One thing I like to do is separately trigger the oscilloscope on different frequency sources in the circuit to see if the measured noise correlates with any of them.  This type of measurement is why good oscilloscopes include an external trigger input.
 

Offline AndyC_772

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Re: How much noise on power rail is normal?
« Reply #13 on: July 12, 2014, 04:18:58 am »
OK, good PCB image, thanks. Can you also please show exactly how and where your probe is connected?

I suspect, as others have already mentioned, that what you're seeing could be more down to the non-ideal nature of a real scope probe than a genuine noise problem in your circuit. Tektronix have a really good app note on probing technique which is well worth a read:

http://circuitslab.case.edu/manuals/Probe_Fundamentals-_Tektronix.pdf
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #14 on: July 12, 2014, 05:10:54 am »
OK, good PCB image, thanks. Can you also please show exactly how and where your probe is connected?

I suspect, as others have already mentioned, that what you're seeing could be more down to the non-ideal nature of a real scope probe than a genuine noise problem in your circuit.

I probed the rail side of C10, C31 and VCC on the pin header. The signal looks roughly the same at all points. I use the little spring provided with the probes for grounding to a point as close as possible to the probing location.

The ripple disappears when I exit receive mode (i.e. disable the 10kHz interrupt / LED toggling). So while the probe might add some ringing, I'm pretty confident the ripple is real.  I'm a lot less confident whether the ripple actually is an issue :)
 

Offline AndyC_772

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Re: How much noise on power rail is normal?
« Reply #15 on: July 12, 2014, 07:29:48 am »
Sounds like you know what you're doing. One possibility is that the source of the noise is the LED current being switched on and off, especially since your power rail appears to be routed rather than being on a plane of its own, so it'll be quite inductive. Try removing the LED and see if that helps.
 

Offline madires

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Re: How much noise on power rail is normal?
« Reply #16 on: July 12, 2014, 08:10:03 am »
Which RF band, which modulation and which protocol? The noise on the power rail could be a red herring.
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #17 on: July 12, 2014, 09:30:48 am »
Which RF band, which modulation and which protocol? The noise on the power rail could be a red herring.

162 MHz (marine VHF), 9600bps GMSK, HDLC - basically an AIS receiver.

Here's the project in detail:
http://forum.43oh.com/topic/4833-potm-daisy-a-simple-ais-receiver/

And its current incarnation looks like this:


One thing I probably should mention is, that the IC does not support GMSK natively. See this thread:
https://www.eevblog.com/forum/beginners/need-some-help-with-si4362-(gfsk-vs-gmsk)/
No idea if that has an impact on sensitivity or is just another red herring. Unlike using a scope probe, I definitely don't know what I'm doing when it comes to RF :)

PS: it's fully functional, I'm in the stage of trying to optimize performance
« Last Edit: July 12, 2014, 09:36:04 am by chicken »
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #18 on: July 12, 2014, 10:17:08 am »
I am very dubious of the out of channel overload capability of these direct conversion receivers.  Insufficient out of channel selectivity could explain the behavior you are seeing.  The RSSI signal strength could just reflect the AGC being pumped by strong local transmitters nowhere near your receive frequency which further lowers the sensitivity.

What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #19 on: July 12, 2014, 10:58:47 am »
I am very dubious of the out of channel overload capability of these direct conversion receivers.  Insufficient out of channel selectivity could explain the behavior you are seeing.  The RSSI signal strength could just reflect the AGC being pumped by strong local transmitters nowhere near your receive frequency which further lowers the sensitivity.

I have a cheap handheld radio (UV-5R+) that can send on the channels in question (A 161.975 and B 162.025 MHz), though no AIS messages. When using it as signal source the received RSSI on the same channel is -10dBm, on the other channel the receiver reports -80 dBm.

The radio specifies "spurious emissions" as < -60 dB. The Si4362 specifies 60 dB adjacent channel selectivity with 12.5 kHz channel spacing. So that seems to be within spec. No idea if that's a good or weak spec :)

Quote
What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.

Will look into this.

Thanks everyone for the great input.
 

Offline HackedFridgeMagnet

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Re: How much noise on power rail is normal?
« Reply #20 on: July 12, 2014, 11:25:53 am »
Quote
The ripple looks roughly the same across the whole rail (close to LDO, close to MCU, close to radio) with a prominent bump roughly every 10ms

10mseconds -> 100Hz.
Maybe linear psu, 50hz mains supply, full bridge rectifier?

Sounds pretty normal.


 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #21 on: July 12, 2014, 11:51:47 am »
Quote
The ripple looks roughly the same across the whole rail (close to LDO, close to MCU, close to radio) with a prominent bump roughly every 10ms

10mseconds -> 100Hz.
Maybe linear psu, 50hz mains supply, full bridge rectifier?

Sounds pretty normal.

My bad, I failed at f -> t conversion. It's definitely 10kHz / 0.1ms
 

Offline madires

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Re: How much noise on power rail is normal?
« Reply #22 on: July 12, 2014, 10:50:56 pm »
Which RF band, which modulation and which protocol? The noise on the power rail could be a red herring.

162 MHz (marine VHF), 9600bps GMSK, HDLC - basically an AIS receiver.

One thing I probably should mention is, that the IC does not support GMSK natively. See this thread:
https://www.eevblog.com/forum/beginners/need-some-help-with-si4362-(gfsk-vs-gmsk)/
No idea if that has an impact on sensitivity or is just another red herring. Unlike using a scope probe, I definitely don't know what I'm doing when it comes to RF :)

I'm no RF expert either, but I'll try my best :) The RF signal strength doesn't tell you anything of the quality of the signal. It may be distorted or mixed with several reflected waves of the same signal and so on. Some modulations are quite sensitive to such issues and other are able to cope with that within some limits. AFAIK GMSK is one of the latter. The demodulation needs some margin to be able to detect the frequency changes of the signal properly. If you're doing the demodulation in software (not the SDR way), I'd think that the required margin is larger than for other methods. Maybe some RF expert could chime in and give us more hints or even some numbers.
 

Offline Christe4nM

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Re: How much noise on power rail is normal?
« Reply #23 on: July 13, 2014, 01:36:31 am »
Hi. I read through the topic and I'd like to chime in regarding noise. I don't know anything useful about RF so I cannot answer if mitigating noise is going to help the RF signal strength issue. Yet I do see some possible noise-related issues in your layout.

So how much noise on power rail is normal?
First of all regarding the amount of ripple and noise that is 'normal': this is purely determined by what the circuit excepts. Example given: if you have 2Vpp ripple on rectified AC before a regulator that might be perfectly 'normal'. Yet your 3.3V MCU has operating limits for the supply voltage so it needs to be within that limits.
That said, it does not mean that you can just leave all kinds of ripple and noise on the supply rail as long as it is say 3.3V +-10%. But noise in itself is not the problem... It becomes a problem when there is an electronic circuit that needs needs to operate and function correctly. Further along the line there are EMC regulations too, to make sure the circuit does indeed behave as intended even with all kinds of noise present. That, and to make sure that your circuit doesn't disturb other circuits as well.

OK, on to some practical stuff. I look at your layout and a few things got my attention. I'll try to keep it not too long as there is plenty of great material already present on the forum.

1) Decoupling cap layout.
First thing to note is that decoupling caps should always be placed between the powersource and the MCU/IC. Also the smallest cap (in value) must be placed closest to the MCU/IC. Why? Well their function is to provide the (initial) current for fast changing loads, giving the regulator time to react to the changing current demand. These fast changing loads are for example your digital communication circuit where every time it switches from 1 to 0 and vice versa the current demanded by the IC from the supply changes. To prevent these changes echoing through the supply the bypass caps are placed to provide that current. Another way to look at it is that they provide a bypass path for high frequency on the supply rail. So those frequencies cannot go beyond the capacitor and enter the supply rail. Note that it works both ways. The IC will no longer 'push' high frequency ripple on the rail, but high frequency ripply won't get to the IC either. This is only part of the picture which I will explain below.

So what you want to do is always place the smallest cap right next to the IC's supply pins, if possible directly over the VDD and GND pins. In other words:  Regulator -> Largest value cap -> smaller value cap -> smallest value  cap -> IC pins.  Make sure the traces always go through the pad of the capacitor. Think of a tollbooth at a highway. You don't want to place that using a off/on ramp, since the majority of traffic will drive right past it. You want to place those tollbooths right on the highway to make sure everyone must go through.

* In your layout you should swap the places of C11+C12 and C10 (if I'm correct to assume that the psysical larger cap is indeed a larger value cap.)
* You should also move C21 so that is sits between the regulator and C22+C23.
* I can't see what C20 is doing, but if it's a bulk or bypass cap, consider moving/rerouting
* Same for C31

2) Why those datasheet values (sometimes) don't work - pt1
What I said above is actually oversimplification of what is going on. In reality it all about the smallest impedance as seen by the frequencies superimposed on the power rails. What you want is that if you have a ripple or noise of some frequency on your rail, that it can be 'shorted' to ground somewhere. Where? well right at the source is the best. How? By providing a path over very low impedance specifically for the frequencies of interest.
This is where the bypass caps come in. Each capacitor has a specific impedance curve over frequency that looks like a V. A capacitor's impedance is very high for low frequencies. That is exactly what we want, since the DC must 'reach' the IC. When we go up in frequency the impedance of the capacitor drops until it reaches the minimum. This is the frequency(range) where it shines as bypass capacitor. Go higher and the impedance actually increases again due to (parasitic) inductance. So in reality that 'rule-of-tumb 100nF' bypass cap, might not do anything at all for the frequency content present in your circuit.
What I tend to do is always leave room for at least one extra bypass cap. That way I can measure the actual ripple and decide to place additional caps later.

3) Why those datasheet values (sometimes) don't work - pt2
Did you know that your 100nF capacitor is not 100nF anymore when put into your circuit? Why? Well the capacity for some capacitors (at least ceramic caps) is voltage dependent. The higher the DC voltage, the lesser the actual capacitance. This results in the impedance curve shifting to lower higher frequencies. Guess what that means for your ripple and noise? Yep, it might not be bypassed anymore as the impedance of the cap for the frequency of interest might actually be in the inductive 'early' capacitive region and much higher than expected.

4) Routing power rail traces - pt1 the journey out
So you want your supply rails as clean as possible. Well in addition to decoupling of noise, you need to route them carefully and away from noise sources. Traces underneath a crystal, oscillator or clock is a big NO. But what about that trace under your MCU? Well, better not do that either. Your MCU is quite a noisy beast, even at low (aka kHz) frequencies. That is due to the harmonic content in digital electronics. It's not just the fundamental frequency, but usually getting up to the 100's of MHz in harmonics. This all depends on the rise- and fall times of the edges of your signals. Even a 1Hz squarewave can generate GHz content of noise if its rise- or fall times are fast enough (sub nanosecond).
In addition you want to keep your 'sensitive' traces away from noise sources. There are rules of thumb for that like 'keep a distance of 5 times the noisy traces' width'. Look that up with your friend Google.

* In your case I'd reroute that power trace away from under the MCU. What you could do is putting a ground pour on the top layer right under the MCU and routing traces on the other side a.k.a. the bottom layer.

5) Routing power rail traces - pt2: where does the return current go?
A good way of thinking when routing your PCB is to think in currents going somewhere. This is because currents always flow in a loop, so it helps you to keep your head in the game by realizing that those currents must go back somehow.
OK, but I've poured a ground, that should do it right? Well, that depends. Try to visualize where the return current will flow though the ground pour/plane. If is has to make a detour to get back to its source, well rather not. If that detour takes it through noisy areas: change your routing.

6) 'Helping' the bypass caps.
It can really help to suppress noise by adding a small resistor (1R or 10R) in the power rail just before the bypass caps. You've now created a low pass filter which enhances filtering. Instead of the resistor a ferrite bead can help too. Don't be fooled by their impedance rating at some frequency: look at their impedance over frequency curve. What you want is something that presents a high impedance or resistance at the frequencies you don't want. Yet at the same time a very low impedance at the desired frequency. For DC that desired frequency is 0 of course.

Phew, this has turned into way more that I intended. Hope this helps.

To the OP:
If it were me I would start with the items I marked with a *. Yes I know, redoing a board isn't that fun: you probably spend quite some time routing it the first time, you are pressed for board space and you have already spend money on the boards and components. Still it might be worth a try.

edit1: typos
edit2: correction in item 3)
« Last Edit: July 13, 2014, 02:14:44 am by Christe4nM »
 

Online tautech

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Re: How much noise on power rail is normal?
« Reply #24 on: July 13, 2014, 02:02:39 am »
@ Christe4nM
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Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #25 on: July 13, 2014, 02:40:57 am »
I'm no RF expert either, but I'll try my best :) The RF signal strength doesn't tell you anything of the quality of the signal. It may be distorted or mixed with several reflected waves of the same signal and so on. Some modulations are quite sensitive to such issues and other are able to cope with that within some limits. AFAIK GMSK is one of the latter. The demodulation needs some margin to be able to detect the frequency changes of the signal properly. If you're doing the demodulation in software (not the SDR way), I'd think that the required margin is larger than for other methods. Maybe some RF expert could chime in and give us more hints or even some numbers.

I have run across this before in FM receiver chains (which includes variations of FSK including GMSK) where RSSI was based on some rectified output from the IF signal chain but "quieting" was measured at the output of the demodulator before data slicing.  High ambient RF and and mixing products would push the RSSI up without any indication of overload from the demodulated output and sensitivity would be compromised.

I would expect a direct conversion design to suffer from this much more and the AGC to add further confusion.  The third order intercept performance of the mixers becomes more important as less RF preselection is available.  The SI datasheet implies some kind of magic at the first mixer but I suspect that amounts to lowering the gain to avoid obvious overload as there is mention of using an AGC.
 

Offline David Hess

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Re: How much noise on power rail is normal?
« Reply #26 on: July 13, 2014, 03:03:07 am »
I have a cheap handheld radio (UV-5R+) that can send on the channels in question (A 161.975 and B 162.025 MHz), though no AIS messages. When using it as signal source the received RSSI on the same channel is -10dBm, on the other channel the receiver reports -80 dBm.

The radio specifies "spurious emissions" as < -60 dB. The Si4362 specifies 60 dB adjacent channel selectivity with 12.5 kHz channel spacing. So that seems to be within spec. No idea if that's a good or weak spec :)
What I think may be happening besides gross overload is that other inputs are mixing in the first mixer to produce noise directly on the frequency you are trying to receive.

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What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.
Will look into this.
I do not know about newer ones but older editions of the Radio Amateur's Handbook had some details about doing this.  Many years ago I designed and built one for 2 meters which made an incredible difference under adverse conditions using the information there and some other sources which are summarized at this link:

http://www.rfcafe.com/references/electrical/helical-resonator.htm

Toko makes relatively inexpensive but suitable helical filters for printed circuit board mounting which cover 163 MHz.  Rough tuning may be done if you have a suitable signal source.  The one I built could handle 20 watts so I initially used a transmitter and SWR meter.
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #27 on: July 13, 2014, 03:09:36 am »
:clap:  :clap:  @Christe4nM indeed! I owe you (and a few others on this thread) a beer.

Re rerouting for ground return path: In the app notes about proper grounding it usually says to avoid noisy return paths to go through sensitive areas. The other way around, sensitive return paths going through noisy areas (like arguably in my design) I didn't see mentioned.

The LDO being at the other end of the PCB makes it tricky to route a separate radio GND path without major detours for some return paths, e.g. the radio/MCU signal lines. In my next layout I could move the LDO to the left, between MCU and radio. Is that the right approach?

No worries about sunk cost or wasted components. I do this to learn something and the prototypes are functional enough that there are willing takers.
« Last Edit: July 13, 2014, 03:21:27 am by chicken »
 

Offline Christe4nM

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PCB layout guidelines
« Reply #28 on: July 13, 2014, 05:33:40 am »
:clap:  :clap:  @Christe4nM indeed! I owe you (and a few others on this thread) a beer.

Thanks, you're welcome. I really like these PCB layout topics. Thinking along and reading other replies really helps understanding this stuff. Fellow forum member free_electron also has posted great posts about several of these topics. That is how I started to learn. Note that I’m still learning. I’m currently working my way through ‘EMC and the printed circuit board’ by Mark I Montrose. So my mind is trying to digest all this stuff anyway.


Re rerouting for ground return path: In the app notes about proper grounding it usually says to avoid noisy return paths to go through sensitive areas. The other way around, sensitive return paths going through noisy areas (like arguably in my design) I didn't see mentioned.

It all comes down to preventing the coupling of noise into the sensitive traces. Routing a sensitive trace under or right next to noisy stuff is in essence the same as putting a noisy trace through a sensitive area. The latter can be compared to the proverbial elephant in a china shop. But you don’t want to stack your china right next to a happily jumping around elephant’s paddock either ;)


The LDO being at the other end of the PCB makes it tricky to route a separate radio GND path without major detours for some return paths, e.g. the radio/MCU signal lines. In my next layout I could move the LDO to the left, between MCU and radio. Is that the right approach?

There isn’t just one ‘right’ approach as I’m afraid.  There are some common steps to guide you though. As you’ll see a layout is almost always a tradeoff between certain best practices. Certainly on a 2 layer board you just cannot help but having to make a compromise here and there. It will help though to take a moment to think it over first.

Even then, I did a over-engineered conceptual 4 layer layout for a very simple, really simple, USB to UART board. I went through several revision before I got the board out. I learned from that, that sometimes it’s just as hard to distinguish what is actually important in your current design as it is to understand all matters that might be going on. That being able to distinguish comes from experience and practice. Something I’m still trying hard to gain anyway :-/O

OK on to the practical tips.

- If your board shape is known, spend some time with paper and pencil to determine which sub-circuits are to be placed where. Draw important signal(busses) too. See Robert Feranec’s video on PCB layout planning for an example of what I mean. (Sorry no link provided since I didn't want it embedded in my post. Just search for "pcb layout planning" on YT) This planning beforehand helps in simple circuits as well as for really complex circuits.

- Connector placement is usually predetermined, so those go as very first. Make sure that after placement of all connectors each cable plug can still fit even if all other connectors are plugged as well. This is a trap as the cable plugs are usually quite a bit broader than the actual connector on the PCB. Placing those connectors to close together could mean that you can't have everything connected at the same time...

- This pre-planning is also where you already think a bit about how/where to place the power rails.

- Since high frequency stuff is the most noisy you want to place and route those components and traces first and keep them as short as possible. I.e. crystals, clock traces, and signals needing a specific controlled characteristic impedance.

- Same goes for communication buses: usually they are busy, higher frequency digital and thus inherent more ‘noisy’. Personally I even try to route them without via’s in the trace, except for possible one very close to the pin of the ICs involved. This is more personal preference and certainly not always possible, but for very high frequency stuff via inductance might play a role. I’m still learning too, so let’s just keep this as my personal preference for now.

- Those higher frequency traces are best if routed above a ground plane / pour. That pour has to be connected to the gnd pins of the IC’s at both ends of course since it will most probably contain the return current. This is because for high frequency the return current seeks the route of lowest inductance. This is actually right beneath the trace. For low frequency this does not apply as those currents seek the path of lowest resistance back to the source. In case of a pcb that is usually the shortest path as resistance increases per length unit.

- As said: keep decoupling caps as close to the pins as possible. Larger, bulk caps can be placed further away.

- Optionally you can rotate the MCU by 45 deg. To make accessing the pins a little easier along the sides of the board. Do whatever works best for you.

- Where you place the LDO is a tough one. It doesn’t need to be that close to any IC as the local decoupling caps will keep the line ‘clean’. I personally would say that the SPI bus from the MSP430 to the RF IC gets priority in routing. What if you push the USB D+ and D- all the way ‘down’? That means they get a bit longer, but also out of the way of the other stuff. You now have an area between the MCU at the left, the USB connector at the right, the USB signal traces at the bottom and the 100mil header at the top. This could be your LDO’s new home?
Your power rail has to cross the width of the PCB one time or another anyway as the MSP430 has its VCC on the ‘top’ as I interpret the layout, and the RF IC on the ‘bottom’. As you have communication buses on both sides of the MCU I think that going under the MCU itself is basically the least worst option. I'd go on the bottom side though and make sure that there is a return path for the current.
Or try both your own idea and mine. See what works best and let us know.

- Semi-Final note. I see that you have a small stub of ground pour between the USB signal traces. That one is best removed as it can pick op noise. If you have other 'stubs', it's good practice to put a via to a ground plane (if available) at the end.

- Final note regarding the USB connector shield and ground tie: that USB to UART board I mentioned was to gain an understanding of EMI, and ESD protection. I made a topic about that in the past, but still have to reply with the final board layout. I'll have to come back to that.

edit: typos
« Last Edit: July 13, 2014, 05:40:07 am by Christe4nM »
 

Online tautech

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Re: How much noise on power rail is normal?
« Reply #29 on: July 13, 2014, 08:52:25 am »
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I really like these PCB layout topics.
Me too.
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spend some time with paper and pencil to determine which sub-circuits are to be placed where.
I have started laying out sub circuits to best final layout(pre-routing), then select all of each sub circuit and drag to an place out of the way and "park" them individually.
When ready for them, drag them back to final position, rotate if needed and  :-/O.
Mostly, only little modification is needed.
If you have sub circuits you use frequently, you can build a library of them.
Avid Rabid Hobbyist
 

Offline AndyC_772

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Re: How much noise on power rail is normal?
« Reply #30 on: July 14, 2014, 12:48:54 am »
1) Decoupling cap layout.
First thing to note is that decoupling caps should always be placed between the powersource and the MCU/IC.
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Make sure the traces always go through the pad of the capacitor. Think of a tollbooth at a highway. You don't want to place that using a off/on ramp, since the majority of traffic will drive right past it. You want to place those tollbooths right on the highway to make sure everyone must go through.

Lots of good stuff here, but I think it's worth elaborating a little when it comes to decoupler placement and routing, because the proper way to position them depends on exactly why they're being used in the first place.

The topology you've mentioned, where a power supply is routed to a cap, and then from the cap to the load, isn't what I'd refer to as a decoupling cap. I'd call it a filter cap, because its function is to filter out noise that's being presented to the load by the PSU. And in that case, I completely agree that your topology is correct.

A decoupling (or bypass) cap is one which exists to supply the short-term current draw from a load whose demand includes high frequency spikes - such as a digital logic device that's switching at regular intervals. In this case, the key criterion is to minimise the inductance between the device pin and the capacitor, for both power and ground. Here it doesn't matter where the cap is in relation to the (dc) power supply, it's getting the inductance down to a minimum that's key.

It's surprising how few PCBs are laid out with this in mind, because there are real benefits to be had from getting it right in terms of EMC. Here's a few tips...

- the lowest inductance path between two points is usually through a solid plane. It may, therefore, often be much better to route from the IC pin to a via, and from the decoupling cap to another via, than it is to route from the IC pin direct to the cap. It's amazing how many engineers have a mental block about this, and insist on routing from the IC to the cap "so the IC 'knows' to get its current from the cap" or some such unscientific gobbledygook. Electrons don't "know" anything, they move around according to the laws of physics.

- most SMD caps are limited in their ability to perform high frequency decoupling not by the cap itself, but by the layout. A really, really worthwhile experiment to do is to look up the typical inductance per mm of a PCB trace, then model that in Spice and see just how much less effective a (say) 10nF capacitor becomes if it has even 1mm of trace attached to each end. Seriously, it's a real eye-opener.

- With that in mind, it can be deduced that one decoupling cap that's connected into a plane with two separate vias at each end is very nearly as effective as two separate caps each of which has only one via. Save yourself some decoupling caps this way.

- Best of all, is to have two small copper planes on the component side of the board at each end of the cap, with multiple vias used to stitch these into the power and ground planes.

- The real benefit of smaller value capacitors is that they come in smaller packages, which have lower ESL. This is why they're generally regarded as being better at high frequencies. You're not achieving anything by putting a 10nF cap where a 100nF cap would physically fit. (I know this point is controversial, but if anyone can show me a convincing argument otherwise then I'm genuinely interested to hear it. Actual measurements of a real board with a suitably expensive impedance analyser could count as convincing!)
« Last Edit: July 14, 2014, 12:51:18 am by AndyC_772 »
 

Offline m12lrpv

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Re: How much noise on power rail is normal?
« Reply #31 on: July 14, 2014, 02:17:29 pm »
Thanks guys for some great information. Plenty to think about that's for sure.
 

Offline Christe4nM

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Re: How much noise on power rail is normal?
« Reply #32 on: July 18, 2014, 05:49:34 am »
<great post about bypass cap layout taking inductance in mind>

Thanks for posting this valuable information. I didn't know this, so I went and tried to find out what known experts say on this (not that you might not be, but just to make sure that others confirm this 8) ) I found that Henry Ott (in his book Electromagnetic Compatibility Engineering) basically says the same, as well as Howard Johnson in one of his articles here.

Now I do wonder if this topology of IC pin directly to reference plane, and bypass cap "via'ed" to plane as well, is still valid or viable (no pun intended) for sub MHz decoupling. Of course the laws of nature don't change, but this topology seems to be mentioned solely in the context of high speed digital, with high speed in this case being >100 MHz. Anyone know this?

My best guess it that it still is, since fast edges are where the bypass caps come in. And those fast edges are containing these high frequency components where that (parasitic) inductance plays a big role.
 

Offline chicken

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Re: How much noise on power rail is normal?
« Reply #33 on: August 15, 2014, 11:15:30 am »
Quote
What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.
Toko makes relatively inexpensive but suitable helical filters for printed circuit board mounting which cover 163 MHz.  Rough tuning may be done if you have a suitable signal source.
I wasn't able to find the part from Toko. But I found this bandpass filter from Mini-Circuits:
http://www.minicircuits.com/pdfs/SXBP-162+.pdf
Is this a suitable filter, or is the <3dB passband of 155-169 MHz too wide?
 


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