EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: LoveLaika on February 18, 2021, 09:20:54 pm
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I'm trying to examine two different SiPM circuits to see how one SiPM affects the other(s) in two different circuits, examining the rise time. Assuming the same SiPM and conditions, the 'Separate' circuit is faster than the 'Array' circuit (in terms of signal rise-time seen at the output); I think that what would affect the timing is the components, so I wanted to ask here and see if my assumption is correct.
In my SiPMs, I'm basing it off of the MicroFJ 6mm sensors from OnSemi via the datasheet below. That's where I got the 3.4 nF capacitance for each SiPM. In 'Separate', there are two SiPMs, each with their own 2nd order low pass filter, connected at the -30 V node. The 'Array' consists of four SiPMs, all connected together at the cathode.
Now, in both circuits, when one SiPM 'activates', because they are connected together at a certain point, the SiPMs will affect the others. In 'Separate', since they are connected at the bias voltage, the effect wouldn't be much, as the signal would have to travel through (essentially) a 4th-order LPF, so there's not much effect (is this correct?). However, in 'Array', since they are connected at the cathode with nothing separating them, you would see an effect in the other outputs. This was mitigated by having C3 be 100 nF (10x the usual 10 nF capacitor), but it seems that the increased capacitance would affect the rise-time of the SiPMs in the circuit. Is this assumption correct? If so, reducing the capacitance of C3 would solve the problem, but the question is by how much?
https://www.onsemi.com/pub/Collateral/MICROC-SERIES-D.PDF (https://www.onsemi.com/pub/Collateral/MICROC-SERIES-D.PDF)
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The rise time of the output (assuming we are talking about the leading edge of the pulse) is affected by the propagation of the signal locally within the chip and how it "secondarily" couples to the output via the other SPADs' capacitances and quench resistors, when you connect many of them in an array, you can get a similar effect except it couples via the array's wiring and so its more dependent on the PCB layout of the array rather than the bias' capacitance.
I believe that the rise time will actually be increased by reducing the capacitance as this give greater bias voltage disturbances and thus greater coupling among SiPMs in the array. I would therefore hypothesise that you could reduce the rise-time by placing smaller capacitances nearer to the SiPMs.
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Thanks for the reply. I'm a bit confused though. You say that you can increase the rise time (longer rise time, slower signal) by reducing the capacitance, but then you hypothesize that I could reduce the rise time (smaller rise time, faster signal) by placing smaller capacitances closer to the SiPMs. I would still be reducing the capacitance at the common cathode node, but because of the way the array is laid out on their PCB (ARRAYC-60035-4P-GEVB), the smaller capacitances would affect all the SiPMs, not just a single SiPM.
https://www.onsemi.com/pub/Collateral/ARRAYC-SERIES-D.PDF (https://www.onsemi.com/pub/Collateral/ARRAYC-SERIES-D.PDF)
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In my "hypothesis" you would still maintain a total "large" capacitance, but distribute it among the elements in the array using many smaller capacitances.
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I see, but since they all share the same cathode via the PCB, you can't distinguish between the individual cathodes of the SiPMs. In this case, would the solution just be to reduce C3 here if you can't distribute the capacitance among the array elements since the net result would be the same? (Focusing on 'Array' here, not 'Separate')
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I'm terribly sorry, I completely misread half your post and had it stuck in my head that you were laying out your own array.
In the case of the array PCBs you are just at the mercy of the layout of the board. Any degradation to rise time will be due to the layout of the board and connectors, C3 (at least the total capacitance on the bias voltage) should be high to keep the voltage stable and prevent any further coupling between channels, its not that which is affecting the rise-time.
...if you were to construct your own array, then I would suggest distributing the capacitance, but that is not possible with those pre-fab array boards.
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Your circuits should not interact much at all. note that the OnSemi (formerly SensL) are prettu awful. We found the Hamamatsu SiPMs to have VASTLY lower dark current, especially if you bias them at the lower end of their suggested range. You get less gain that way, but the dark current noise goes even lower. Note that you want your preamplifier to present as low as possble impedance to the SiPM.
Jon
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Your circuits should not interact much at all. note that the OnSemi (formerly SensL) are prettu awful. We found the Hamamatsu SiPMs to have VASTLY lower dark current, especially if you bias them at the lower end of their suggested range. You get less gain that way, but the dark current noise goes even lower. Note that you want your preamplifier to present as low as possble impedance to the SiPM.
Jon
Just out of interest, when did you do the comparisons? It was just that around 2014 or so the opposite was the case and it was just when SensL changed fabrication methods and achieved dark currents than Hamamatsu that I was involved with them... so I'm wondering if Hamamatsu have upped their game since.
Also forgot to add that any slowing of the rise time is only a small fraction of the few ns they are individually, but the chances of finding my original notes for accurate numbers are pretty slim.
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Thanks for your reply penfold. With the array, I ran some tests using a board I made. I ran tests with C3 at 10 nF and 100 nF. At 10 nF, my signals were fast (picoseconds), but there was coupling. With the 100 nF, there was no coupling, but the signal was slower (in the nanosecond range). I should apologize as well; I think I have been judging my signal speed on the rise-time, but maybe that's not the best metric to go by. Nevertheless, from this test, 10 nF is too small and 100 nF is too large. When trying to find 'just right', is it just trial and error?
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Can you measure with an oscilloscope the voltage on C3 (with the shortest possible ground lead) for both the 100nF and the 10nF preferably when synchronised with a "pulse" event? Would also be interesting to see if there's much of a bias variation immediately on the array's connector (but that's much harder to probe without introducing more problems).
I was never very impressed with SensL's boards or connector choices (in defence of SensL they weren't happy either, but *reasons* prevented them changing at the time). It might just be worth checking with OnSemi that the array module you have is suitable for the timings of your application, I personally wouldn't use the 8pin DIL its mounted on for nano- let alone pico-seconds.
I think I have been judging my signal speed on the rise-time, but maybe that's not the best metric to go by.
And just to double check.. you are definitely referring to the rise-time of the leading edge of a positive going pulse and not the aren't you? Thats absolutely the correct parameter to use if so.
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Your circuits should not interact much at all. note that the OnSemi (formerly SensL) are prettu awful. We found the Hamamatsu SiPMs to have VASTLY lower dark current, especially if you bias them at the lower end of their suggested range. You get less gain that way, but the dark current noise goes even lower. Note that you want your preamplifier to present as low as possble impedance to the SiPM.
Jon
Just out of interest, when did you do the comparisons? It was just that around 2014 or so the opposite was the case and it was just when SensL changed fabrication methods and achieved dark currents than Hamamatsu that I was involved with them... so I'm wondering if Hamamatsu have upped their game since.
Also forgot to add that any slowing of the rise time is only a small fraction of the few ns they are individually, but the chances of finding my original notes for accurate numbers are pretty slim.
Well, interesting info, thanks! I think we were working with the SiPMs around 2019, maybe into early 2020. We used the SensL parts with the fast and slow outputs.
Jon
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Thanks for your reply penfold. With the array, I ran some tests using a board I made. I ran tests with C3 at 10 nF and 100 nF. At 10 nF, my signals were fast (picoseconds), but there was coupling. With the 100 nF, there was no coupling, but the signal was slower (in the nanosecond range). I should apologize as well; I think I have been judging my signal speed on the rise-time, but maybe that's not the best metric to go by. Nevertheless, from this test, 10 nF is too small and 100 nF is too large. When trying to find 'just right', is it just trial and error?
It may be that the ESR of your larger cap was higher than the smaller one. That's the only thing I can think of that could cause what you saw.
Jon
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Thanks penfold. Sorry, not able to view it due to size limitations. Tight fit in working environment.
Going back to what you said, designing your own arrays, distributed capacitance amongst each of the SiPMs would definitely help, but in doing so in order to form an array, assuming that they are not shorted with each other, would cathodes and anodes of different SiPMs affect each other if they were put close to each other, or would the capacitors help mitigate that?
Here's what I mean. Looking at the layout of the C-series SiPMs, cathodes and anodes are diagonal from each other. Sometimes, with layouts in arrays like a 2x2 array or larger, you may come to points where an anode of one SiPM would be next to an anode or cathode of another SiPM. Would they affect other somehow being that close?
https://www.onsemi.com/pub/Collateral/MICROC-SERIES-D.PDF (https://www.onsemi.com/pub/Collateral/MICROC-SERIES-D.PDF)
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Going back to what you said, designing your own arrays, distributed capacitance amongst each of the SiPMs would definitely help, but in doing so in order to form an array, assuming that they are not shorted with each other, would cathodes and anodes of different SiPMs affect each other if they were put close to each other, or would the capacitors help mitigate that?
Here's what I mean. Looking at the layout of the C-series SiPMs, cathodes and anodes are diagonal from each other. Sometimes, with layouts in arrays like a 2x2 array or larger, you may come to points where an anode of one SiPM would be next to an anode or cathode of another SiPM. Would they affect other somehow being that close?
Well, first point is to work out whether or not you really need that extreme a rise time, I'm assuming you do, but just thought it prudent to make sure you're not chasing anything unnecessarily.
The answer is yes and no, good PCB layout is an essential factor, by decreasing the overall impedance of the bias source (local capacitors and bias distribution as a power plane) you also reduce the ability of the other signals to indirectly couple on to the bias, so that's one factor (which I think is the more significant one); the intrinsic proximity of the terminals in an array probably isn't a significant coupling capacitance in itself when compared with the possibility for coupling between the signals' PCB traces (which careful layout can mitigate) and the fact that the resistances are generally quite small.
Also worth bearing in mind would be the fact that (of course depending on your optical setup) that it doesn't take many stray photons from the "main event" to activate other elements in the array making it look like there's electrical coupling when it may just be optical.
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Thanks for your reply. Reducing the impedance through the use of a plane...well, running through a test layout, I was hoping to keep it at a 2-layer board and route the bias to the necessary points through 20 mil traces. Definitely, for sure, with each SiPM having their own 2-stage LPF, the capacitors are right next to their respective cathodes, so like you said, problem is with the traces themselves. In my test layout, I kept all traces on the bottom layer, and the anode signal layers aren't routed all over the place (routed rather close to their respective outputs), so perhaps I am okay for now. Thank you for reminding me about the plane as an option. I wanted to avoid using a plane as that would require me to put vias in an already constrained space.
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Thanks for your comments Jmelson. Through our tests, we found that pre-amps made our signal slower, so we decided to omit them and read out the SiPM's current signal as indicated by the schematic. I'll admit, this isn't the way SensL recommended. The way we had it set up (Fig 13 in the PDF below), it was like that, but we just removed the op-amp and shorted the feedback loop, so you have just a resistor in series with the SiPM which goes to the output to be read out (rather than have a sense resistor in parallel like in Figure 14).
Actually, thinking about what you and Penfold said, specifically about his comments involving reducing impedance to improve rise time, looking at the linked document, turns out that I think I may have a way. The output resistor from the anode to the output connector (to go off-board), can be reduced, and SensL even encourages it in Fig. 14, using 10 ohms instead of 50 ohms. I've been using 50 ohms, and this simple change may improve everything. Granted, I'm reading it out differently than how SensL intended, but it's the only way I can think of to reduce impedance.
https://www.onsemi.com/pub/Collateral/AND9782-D.PDF (https://www.onsemi.com/pub/Collateral/AND9782-D.PDF)
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Penfold, sorry, but I wanted to ask about a difference between the readout methods. As shown in the previously linked document for readout methods, you could read out an SiPM by either using an op-amp to convert the voltage or not use one at all. Looking at Figure 13, the 50-ohm resistor before Vout, is it there for impedance matching (assuming a 50-ohm transmission line)? Why would the SiPMs in figure 14 (without the op-amp) not require an impedance matching resistor if in both cases you're reading out the voltage? Would it be good practice to include one to prevent reflections? Running some simulations, it seems that including one would reduce the voltage amplitude and affect the rise time.
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In figure 13, the series resistor is doing a few things things, one of which will be impedance matching, the output of the TIA will be low impedance and a series resistor can be used to match its impedance to the cable (assuming 50 ohms cable)
w.r.t. figure 14, an approximate model for a SiPM/APD is a current source, having a high impedance and occasionally letting through "blips" of current, the output impedance of the network in fig. 14 is therefore Rs in parallel with the "equivalent parallel resistance of the SiPM", assuming Rs << R_SiPM then the output impedance is approximately Rs... 50 ohms in that case - which should match with the cable nicely and no need to add anything in series.
Whether or not you need impedance matching (for Rs other than 50 ohms) is very application specific and depends how you implement it. If you have a large mismatch between source impedance and cable then you need to start viewing the cable as a component in itself containing capacitance and inductance and it becomes difficult to simulate well, SPICE will get you somewhere near, but I wouldn't be totally confident in it especially in the pico-second end of the spectrum.
The "fast output" being capacitively coupled off the internal resistances has a few more complexities to its impedance and varies a little bit during dynamic conditions, which is where the balun on figure 22 comes in to play to help control its impedance a little, I don't recall any specific problems with the SensL implementation of the fast output and recommended balun, but with that I was dealing with Cherenchov detection (rise times were closer to ns), so any serious artefacts would have been over before the peak of the pulse.
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Thank you for your insight. For the moment, we're just reading the voltage coming off an active SiPM using 50-ohm impedance coaxial cables over a short distance. I don't believe the SiPMs would have a small impedance; that doesn't sound right. But, yes, like you said, EPR would be seen here as Rs // R_SIPM. It's unfortunate that SensL/OnSemi doesn't mention equivalent resistance for their product, but seeing as how they show 50 ohms at the respective outputs, looks like it's fine as you said. It's interesting how they recommend 10-ohms for reading out 6mm sensors in Fig. 14. In that case, we would see an impedance mismatch assuming a 50-ohm cable and steps must be taken accordingly?
Again, thank you very much for your insight and comments.
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I don't believe the SiPMs would have a small impedance; that doesn't sound right.
...large impedance... they are only diodes in reverse bias, so the actual ohmic resistance is very high (>100k for all in parallel), far bigger than any useful load resistance,
It's interesting how they recommend 10-ohms for reading out 6mm sensors in Fig. 14. In that case, we would see an impedance mismatch assuming a 50-ohm cable and steps must be taken accordingly?
There is a bit of voodoo involved in selecting the best Rs; with a 6mm sensor - using 10 ohm in preference to 50 ohm will combat some of the higher capacitance (higher when compared with a smaller area sensor) which would otherwise degrade your rise-time which is why I think that's what they suggested in the datasheet. I can't really advise you whether or not you *need* the impedance matching without seeing any existing results or knowing where the signal is going, I would say you *should* take measures to match to the cable impedance (but you may not *need* to). It would also depend if you are more interested in just timing or pulse shape, if can you share a little more about the project and I may be able to be more specific.