Basic PCB design questions

[jgalak]

I've designed PCBs before, mostly PTH, but a few SMD ones, too.  However, these were all very basic boards.  Little more than breakouts for a single SMD part, with maybe a few additional components, like decoupling caps.  I'm now working on a more complicated board, and have a few questions about best practices.

1) Is it ok to place a via on an SMD pad?  The software lets me do it, and it's often a very convenient place, but I'm wondering if the part will be solderable with the via there.  I plan to mostly use a toaster oven and solder paste, for reflow, if that matters.

2) Is it ok to run a trace under a larger SMD part?  I don't mean on the back of the board, I mean right under the chip, on the same side.  Perhaps even place a via under the chip?  Obviously not possible for chips with a central ground pad, but what about for ones that don't have them, like an ATMega328p in a TQFP-32 package?

3) Are there books/articles/etc. out there on making the designs look better?  I'm pretty sure mine will work, electrically.  It's just ugly as sin - components all over the place, traces running every which way, etc.  Especially compared to professional boards which tend to be very neat and organized looking.  I suspect the answer is "look at more boards and design more boards, this will come with practice", but perhaps there are good teaching materials on this.

Thanks.

[phil from seattle]

What design SW lets you put a via in an SMD pad? Eagle doesn't (with typical design rules).  Have you run design rule checking?

Traces under SMD parts. Yes, you can do it.  Though I would recommend being judicious about it and it does depend on the part. SOICs, yes.  402 resistors, no.

There are lots of web pages on how to do PCB layout. Here's one.  But, there is no substitute for learning by doing. Why don't you post your board for some constructive feedback? In the past people have been pretty reasonable and helpful on this forum. Everybody had to start somewhere.  I know my first attempts were pretty cringe worthy.

[jgalak]

Kicad allowed me do it.  Not sure if that's an error on its part or mine.   Still don't know if this is ok - will the via prevent soldering?

I've gone through the Sparkfun tutorials (as well as the Contextual Electronics one for KiCad) - that's how I learned to do this originally.  But none of them address significantly more complex boards.  Not that mine is super complicated, but more so than the one in that tutorial.  The one I'm working on right now has 54 components, including a TWFP-32 IC and a QFN-20 IC.  Trying to get them onto as small a board as possible.  Which makes things....messy.  And this is just an intermediate step - the final board will have more parts, there's at least a few more "blocks" I will need on the final version. 

I absolutely intend to post the board once I've gotten a little bit further in working on it.

[phil from seattle]

sounds like you're going in the right direction. What did Kicad design rule check (not sure that's the kicad term) say when you ran it?

Anyway, a couple of thoughts:
- Don't worry too much about making your board super small. A really tight layout makes debugging harder.
- Group your components into "arrays". Line up your components. Avoid (seemingly) randomly scattering them about the board. Make your board look neat and tidy. A sloppy layout is the sign of a sloppy designer.
- Use test points to allow access to important signals when no other ways exist. Think through test and debug before you finalize layout.
- Think about your enclosure before finalizing your board. Where will the external connections be made? Display, buttons, knobs, indicator openings? How will you assemble it? I'd pick the case first and design the board to fit it. Think about people will be using it. If it's hand held, simulate using it to get a sense of usability. Nothing is more a PITA than trying to find a case that works as an afterthought.

[tooki]

Isn’t it normal to place vias for thermal purposes on large thermal pads (like on a D-pak or QFN) to thermally bridge to a big plane on the opposite side of the board?

But I don’t think it’s considered a good idea on any other pads.

[phil from seattle]

Isn’t it normal to place vias for thermal purposes on large thermal pads (like on a D-pak or QFN) to thermally bridge to a big plane on the opposite side of the board?

But I don’t think it’s considered a good idea on any other pads.

This got me thinking about vias in pads.  I've used lots of thermal vias and it makes sense to have them as close to the head source as possible. Don't think I've seen layout recommendations with vias actually in the pads.  Here's a  TI application report on PowerPAD (I think that's their name for a slug). It's sort of a pad but treated differently. They put vias under it.  The way to do this in PCB design would be, instead of a pad, to just create copper and solder mask polygons that you could place vias in.  To force electrical connection to gnd, you could put a small pad within the polygon opening (with no thermal relief). I'd put that in the library part itself. Doable in eagle, not sure about kicad.

[phil from seattle]

Found another document, from a board house. This talks about solder wicking as an issue.

[David Hess]

The obvious problem with a via collocated with a pad is that it will wick the solder into it leaving insufficient solder for the part.  This can be handled by making the pad and stencil larger so the via fills up leaving enough solder for the part.

[T3sl4co1l]

Outside of a production environment?  Do whatever the hell you want, in fact, try different things and see for yourself what works best.

Via-in-pad is fine for hand soldered parts -- simply apply solder as needed.  It's less good for paste and reflow, where the solder amount is limited.  Less still for hidden pads that you can't inspect or retouch (QFN, BGA, LGA).  (One trick for QFNs, use a single humongous via in the middle so you can touch the part underside with an iron, and inspect the joint.)  And the worst for very small components (typically 0603 and below) which may be prone to tombstoning as a result of uneven melting or solder balance.

Tim