EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: MarkS on November 02, 2024, 09:20:42 pm
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I have an idea for a "simple" retro computer design where every subsystem, memory, CPU, I/O, video, etc, would be on a seperate daughter card plugged into a backplane so that I could experiment with the subsystems without having to redesign everything. I know that ringing on the traces is an issue and that termination resistors are the cure, but I am having a difficult time finding resources that explain how to choose them. I would want this to work with a range of 10 MHz to 66 MHz. I don't mind figuring it out for myself, but I cannot afford to make multiple prototype revisions. This cannot be trial and error.
How do I do this?
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Termination resistance will depend on the impedance of the traces and any necessary biasing. So for instance TTL common in old systems use Thevenin termination of 220 ohms to +5 volts and 330 ohms to ground. CMOS could use Thevenin termination but AC parallel termination is recommended.
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Termination resistance will depend on the impedance of the traces and any necessary biasing. So for instance TTL common in old systems use Thevenin termination of 220 ohms to +5 volts and 330 ohms to ground. CMOS could use Thevenin termination but AC parallel termination is recommended.
Thank you. I thought it was frequency based, not impedance.
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I have an idea for a "simple" retro computer design where every subsystem, memory, CPU, I/O, video, etc, would be on a seperate daughter card plugged into a backplane so that I could experiment with the subsystems without having to redesign everything. I know that ringing on the traces is an issue and that termination resistors are the cure...
You can try what was done in the past.
The S-100 bus of the 1970s was formalized as IEEE 696. Have a look at sections 3.4 and 3.7 in the spec.:
http://www.s100computers.com/General%20Images/IEEE_696_1983.pdf (http://www.s100computers.com/General%20Images/IEEE_696_1983.pdf)
Open-collector lines have a 360 ohm pullup resistor to +5V.
Actively driven lines have a 180 ohm termination into 2.6 V. You can implement this as an active termination (voltage source with series resistors)
or an equivalent resistive divider (a post above describes it). Note that the drivers shouldn't be too fast (5 ns rise/fall time min. - section 3.3).
On the SCSI-2 single-ended bus, terminations were often similar - active termination or resistive divider equivalent.
A more advanced style is to use schottky diode termination. You may not need this yet, but so you know for future reference, in the SCSI community
this was called "forced perfect termination" (FPT). See figure 6 for the concept:
https://www.t10.org/ftp/x3t9.2/document.91/91-037r0.pdf (https://www.t10.org/ftp/x3t9.2/document.91/91-037r0.pdf)
The idea is to terminate each line with two voltage sources via series diodes. When the signal on a line goes high, one schottky diode clamps it to
near high voltage (say 2.1 V), limiting overshoot. When the signal goes low, the other schottky diode clamps it to near a low voltage (say 0.7 V),
limiting undershoot.
It's an idea that came from ECL technology. Some S-100 bus motherboards used it as well.
The technical advantage of diode-style termination, with its non-linear resistance, is that it can be more tolerant of variations in line impedance. The idea is,
if the diode impedance is too large for the incoming reflection, it turns the diode on harder, reducing its impedance. So the diode "adapts" to the conditions
on the line.
See section 1 of the S-100 spec.:
* max. of 22 devices on the bus;
* total interconnected path no more than 25 in (63.5 cm);
* max. switching rate no more than 6 MHz.
Some S-100 builders resorted to the ECL/FPT termination technique so they could drive the bus at faster rates. So it may be relevant to you later.
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Correct type of termination depends on drivers and receivers. For example, for usual single-ended logic signals (CMOS or TTL level) no termination at all or series (source) termination is used.
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I've been doing more research on this and I'm still really confused. In the attached image, I show two examples of active termination circuits that I've found. In the first (left) case, how is this not a direct short to ground? I've also seen the second (right) case with a mystery capacitor of unknown value doing... something? :-// The capacitor is troubling to me as well. If the ESR is too high, I have a very oddly designed voltage divider, which is not wanted. If the ESR is too low, it becomes the path of least resistance, and thus another direct short to ground. Even is there is a magic combination of ESR and uF values, how does this not turn the circuit into a RC circuit? Is that the goal? If so, what time constant am I shooting for?
Please offer some clarity. I feel this shouldn't be so difficult or mysterious. Clearly I'm not understanding something.
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I think the answer just occurred to me! Each bus line isn't grounded individually. They are all grounded through the 2.6v voltage source. In my case, that's a linear voltage regulator. Essentially, I take it that I am powering the bus lines with a 2.6v source through 180 Ohm resistors?