Electronics > Beginners
How to choose Mosfet resistor values for biasing and gate protection?
jnz:
I found a really long stackexchange post on this, and some other data but got lost in the weeds.
See attached pic. I'm trying to hold that 5V DEVICE pin low all the time except when the micro decides otherwise, including the scenario the micro is not powered or has no code. I have up to 100mS to switch when it needs to happen. Something like this small transistor: https://www.mouser.com/datasheet/2/348/ru1j002yn-e-1018335.pdf]https://www.mouser.com/datasheet/2/348/ru1j002yn-e-1018335.pdf
Gate resistor:
I think I need a gate resistor on the right side of the pullup closer to the mosfet. For gate protection, but as I understand this it's more micro protection because an unpowered mosfet will appear like ground to the micro for a short moment and the gate resistor is to slow this process down. So if I have a 5V micro that can source 20mA, I want something like a 250ohm resistor here to stay at that limit so long as the switching speed is acceptable
So... On that... I won't ever see the mosfet as "ground" because it'll never be unpowered, the biasing weak pullup is there. How do I determine an appropriate value for the gate resistor?
Bias resistor:
Next, when I turn this mosfet off by grounding the gate, I'll be leaking 50uA into the ground keeping the weak pullup down. This is more than 1/2 the "sleep" current I'm shooting for. Just how weak can I make this pullup? Can I "get away" with 200k? I don't know the line capacitance so I assume I can't really determine this effectively. Is there a general rule for acceptable mosfet gate bias resistor values?
spec:
Hi jnz,
The value for the pull up resistor is limited by the gate leakage current, which for the RU1J002YN small signal NMOSFET is quite high at +-10uA. So a 100k pull-up resistor may only pull up to 4V rather than 5V which would still be OK. But I would be inclined to find another NMOSFET with lower gate/substrate leakage current if you want to use a higher value of pull up resistor to reduce static current consumption. If I get time, I will have a look too. If you really want to reduce static drain current there are techniques to do this but the circuit would be more complicated.
In slow applications like this, the gate resistor (gate stopper) prevents the NMOSFET from oscillating due to the NMOSFET's high frequency response and relatively large parasitic capacitances. A good starting point for gate stoppers in slow applications and with low parasitic capacitances (for a MOSFET) is from 10R to 500R, with 50R being a good choice. For high power MOSFETs, with parasitic capacitances of nF, a gate stopper of 1R to 22R would be more appropriate for slow applications. Note that the gate stopper must be physically mounted on the MOSFET gate terminal (or within a couple of mm) using as short a leads as possible.
Just a cautionary note. The higher the resistance value of the pull up resistor, the higher will be the impedance of the MOSFET gate node which will become more susceptible to electrostatic pick-up, so a good layout is essential and, possibly, screening may be required. A decoupling capacitor from the MOSFET source to the 5V supply close to the MOSFET would also be advisable.
https://www.mouser.com/datasheet/2/348/ru1j002yn-e-1018335.pdf
(there is a bit more about gate stoppers in this thread: https://www.eevblog.com/forum/projects/circuit-for-mosfets-in-parallel-for-extra-current-capacity/msg2082850/#msg2082850)
spec:
Hi again jnz
There are quite a few small-signal NMOSFETs with gate threshold voltages around 1V and gate leakage currents of around 100nA (as opposed to 10uA). A good example is the Diodes DMN2990UFZ. With this NMOSFET you could have a 1M pull up resistor and a recommended gate stopper of 47R, 50R, or 56R, so the static drain current would be reduced from 50uA to 5uA.
Note though that the above is dependent on the microcontroller input/output pin leakage current being no more than 1uA. This will need to be checked from the microcontroller's datasheet.
https://www.diodes.com/assets/Datasheets/DMN2990UFZ.pdf
T3sl4co1l:
Depends on the MCU pin characteristics. Some are clamped to VCC with diodes, others are clamped with zeners from ground. The latter is usually a "5V tolerant" type on lower-supply MCUs.
Tim
David Hess:
--- Quote from: jnz on January 01, 2019, 09:03:30 pm ---I think I need a gate resistor on the right side of the pullup closer to the mosfet. For gate protection, but as I understand this it's more micro protection because an unpowered mosfet will appear like ground to the micro for a short moment and the gate resistor is to slow this process down. So if I have a 5V micro that can source 20mA, I want something like a 250ohm resistor here to stay at that limit so long as the switching speed is acceptable
So... On that... I won't ever see the mosfet as "ground" because it'll never be unpowered, the biasing weak pullup is there. How do I determine an appropriate value for the gate resistor?
--- End quote ---
The gate of an unpowered MOSFET always looks open with its normal input capacitance.
I select the gate series resistor to limit the peak current through the I/O pin so somewhere between 1mA and 5mA or 4.7k to 1k but 220 or 270 ohms will work fine also.
--- Quote ---Bias resistor:
Next, when I turn this mosfet off by grounding the gate, I'll be leaking 50uA into the ground keeping the weak pullup down. This is more than 1/2 the "sleep" current I'm shooting for. Just how weak can I make this pullup? Can I "get away" with 200k? I don't know the line capacitance so I assume I can't really determine this effectively. Is there a general rule for acceptable mosfet gate bias resistor values?
--- End quote ---
That is always a problem. The issue is leakage from the MOSFET and leakage from the circuit construction so the environment is important.
The gate leakage specified in the datasheet reflects how the power MOSFET was tested and not its actual performance so it will certainly be much lower. That makes 200k or even 1M feasible in most cases.
But if you want to be sure and maintain the lowest power draw, then some kind of active pull-up which can be disabled is called for. This might be as simple as an external CMOS gate which is always powered.
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