How to connect this TCXO oscillator?

[soFPG]

My CPU of choice needs a 13MHz clock signal from a TCXO, input voltage for the TCXO is 2.8V.
I chose the STO-3225A from Siward (http://www.siward.com.tw/uploads/Pro/74/Pro_DM/_P1-72_39.pdf).

My problem now is that I don't know which passive components it needs to function correctly (I have never used a VTCXO before).
What is irritating to me: pin 1 is described as "Tri-state" but what's the actual function of that pin?

Any help is very much appreciated.

[james_s]

That is an odd way of describing that pin, I don't think I've ever seen that on an oscillator. I suspect it is an enable pin though, many times it can be left floating and the oscillator will run by default. You might look for a better datasheet for a similar oscillator in the same package style, the pinout seems to be fairly standardized.

[soFPG]

That is an odd way of describing that pin, I don't think I've ever seen that on an oscillator. I suspect it is an enable pin though

Enable-pin means it is connected to VTCXO as well (as Pin 4)?

I assume that all TCXO oscillators are basically the same - so is there a general circuit for them?

[ArthurDent]

"three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels. "

[wraper]

IMHO it's not connected described in weird way.

[soFPG]

"three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels. "

I know what tri-state means, just not in the context of a TCXO-pin

IMHO it's not connected described in weird way.

So it should be left open?

[wraper]

Crystals and oscillators usually have what you could consider as "industry standard" pinout. Here is another TCXO in 3225 package https://ecsxtal.com/store/pdf/ECS-TXO-3225.pdf. Pin 1 is NC for plain TCXO variant.

[wraper]

IMHO it's not connected described in weird way.

So it should be left open?

Should be fine if left floating or connected to GND.

[Ian.M]

The very similar STO3225-B uses that pin for tristate control: ground it to disable the output.  See http://www.siward.com.tw/uploads/Pro/77/Pro_DM/_P1-72_51.pdf

It should be OK left floating but may need to be tied high.

The manufacturer's test circuits are here: http://www.siward.com.tw/en/technical_info.php?Tec_ID=11
Note the 0.1uF decoupling cap across pins 2 and 4.

You've chosen the STO-3225A which is the clipped sine output version.  It certainly wont provide a good rail to rail output (worst case it only guarantees 0.8V pk-pk output), so depending on your specific CPU's requirements you may need to square the STO-3225A output up with a carefully biassed buffer or fast comparator.  It may actually be easier to simply get one with a rail-to-rail CMOS output. (see http://www.siward.com.tw/en/technical_info.php?Tec_ID=10 )

[soFPG]

Here is another TCXO in 3225 package https://ecsxtal.com/store/pdf/ECS-TXO-3225.pdf. Pin 1 is NC for plain TCXO variant.

Should be fine if left floating or connected to GND.

The datasheet you just linked to says "NC or Vcont" - not GND?

It should be OK left floating but may need to be tied high.

Okay, tied to Vcc makes more sense to me than to GND

The manufacturer's test circuits are here

Does "test circuit" mean this is used to test the correct functionality of the TCXO (but not required in the final product) or is this the circuit required for the TCXO to function correctly?

It may actually be easier to simply get one with a rail-to-rail CMOS output

Thanks!

depending on your specific CPU's requirements you may need to square the STO-3225A output up with a carefully biassed buffer or fast comparator.

The datasheet of my CPU actually says that there is a "Clock Squarer" right after the SYSCLK input - so I guess it should be fine just using the clipped sine wave?

Edit: I found a document about VTCXO recommendations for my CPU and the manufacturer listed "TOH2600DPI4CNP" (http://www.quartz1.com/price/PIC/407N0095613.pdf) as "OK". It has the same characteristics as the TCXO mentioned in my first post (Clipped Sine Wave, 0.8Vp-p Min) besides the fact that it creates a 26MHz clock (which is fine, the CPU accepts 13 and 26 MHz). So I guess I will stick with the one in my first post unless I shouldn't?

[soFPG]

Is this sufficient?