Mixed signal board: split or single ground polygon?

[Sparker]

I know that this topic is old as hell  , some recommend to have analog and digital ground, others recommend having a single polygon. I'd like to have some advice regarding my PCB.

So, what I have is: two-layer board, 3xAD7685 ADCs chained with serial interface, an STM32 MCU and an Ethernet PHY. The ADCs are at the top of the board, Ethernet is at the bottom, MCU is in the middle, and power supply is at the bottom left. Initially I thought to split the grounds, as shown on the picture, leaving a single bridge under the tracks of the serial interface. But I've seen it many times at this forum that it's better just to have one polygon.

What should I do? 

[ejeffrey]

The answer is old as hell too: regardless of ground plane design, the most important thing is to keep your analog signals and digital signals and their return paths separated from each other in your layout.  If you do that properly, then considering your circuit in isolation there shouldn't be any current flowing across the boundary so it doesn't matter if there is copper there or not.  If you do it wrong, your circuit will perform badly in either case.

There are at least two important caveats to this:

A plane of metal with a slot cut out of it is an antenna.  So for EMC purposes, a solid ground plane is preferable.

For low frequency / precision DC the return currents are not so well confined by the path of least inductance.  A split plane can help in this case.

Generally I am in the "use a single ground plane" camp unless you are absolutely sure you need to split it.

[abraxa]

From the pictures it's a little  hard to see what's going on in the upper half but it *seems* as if the serial lines shared between the top and the bottom span quite a stretch across the top part and also the bottom part. This could allow them to pick up energy from the bottom half and transmit them to the upper half. I'd say it's unfortunate that you placed the STM32 in such a way that the used ADC pins are at the bottom, not the top. Now you not only have two ADC interface traces form half a loop, they also run right into the area with lots of digital I/O (think of the ground currents) and even run in parallel to some of the ethernet I/O for a bit.

I'm not an EMC expert myself but if EMC is of concern then it *might* be worth to consider adressing this. Turning the STM32 by 180 degrees would essentially mean to re-do the entire layout, though...

[Sparker]

Thanks for your feedback!

abraxa, you are right, the ADC serial interface traces run as you have described. Unfortunately there is not much I can do about it. If I flip the MCU 180 degrees, then the whole high-speed bus for the Ethernet would have to run around somehow, and I must place the Ethernet jack as shown on the picture, that is, facing up (or down) along the vertical axis of the board. EMC certification is not of concern, I just don't want the digital noise ruin my signal which is fed into the ADCs, so I keep Ethernet and ADCs away from each other. Here is a better picture showing the ADC interface lines. Sorry for the bad quality in the other picture.

For low frequency / precision DC the return currents are not so well confined by the path of least inductance.  A split plane can help in this case.

What is not very clear for me about the split plane design in my case is , since I have inserted this bridge between the planes, will the DC current of the ADC domain return to the power supply through its own plane on the left at the top side(check picture of the first post), or through the bridge and then through the plane of the MCU domain? I guess it would go partly both ways, so does splitting planes make any sense in my case?  I guess not. What do you think?
In my application I care about the band of DC...300 kHz or so, which is almost DC.

[abraxa]

What is not very clear for me about the split plane design in my case is , since I have inserted this bridge between the planes, will the DC current of the ADC domain return to the power supply through its own plane on the left at the top side(check picture of the first post), or through the bridge and then through the plane of the MCU domain? I guess it would go partly both ways, so does splitting planes make any sense in my case?  I guess not. What do you think?
In my application I care about the band of DC...300 kHz or so, which is almost DC.

The DC return current isn't of relevance here since it doesn't create a changing magnetic/electric field that can influence other traces, so there's no need to worry about where the DC return current flows. The supply current is of much greater importance but from what it seems you already have added bypass caps to each ADC. Adding a ferrite bead to the ADC supply line also doesn't hurt, not sure if you have that already or not.

Where does the 300 kHz figure come from? Is that a clock frequency? Keep in mind that it's not the clock frequency that determines the highest frequency to be concerned about but it's the rising/falling edges - their slew rate determines the frequency components you'll see across the traces.

If you're really very concerned about ADC performance even before measuring it, you could always add footprints for passive filters to the ADC I/O lines. If you find that the performance is not as good as you need it to be, you can then add filter components to these footprints. Those should filter out any "high" frequency components relative to the signal you need to see. It's not something I see often but it is doable if the signal and noise frequencies are far enough apart.

[Sparker]

300 kHz is an approximate frequency band of my signal which is fed into the ADCs. To be more precise, it's going to be a 240 kHz narrow band signal. I mostly worry that the Ethernet circuitry will interfere with my analog signal somehow because of poor ground design when Ethernet starts transmitting. But I don't see a direct route for such interference right now, except for high speed Ethernet<->MCU data bus leaking out due to 2-layer board design and slots in the ground polygon under the traces of this interface. 

Thanks, that is an interesting idea to add the filters. Although I am not totally sure how important this is because the ADCs use internal clock for conversion. After the conversion is done, I apply external clock to shift the bits out through the serial interface. So conversion and interface operation are separated in time.

[max_torque]

I guess the other question is "how little noise do you need"?  You have a 16b ADC, and some reference voltage (presumably 5, 4.096 or 3.3 v etc) so you know what your theoretical maximum resolution is, and depending on the performance of your voltage reference you can make a stab at estimating how many bits worth of noise you can cope with, and depending what signals you are measuring, you may be able to add suitable analogue or digital filters to improve the SNR?

[Sparker]

Of course, 'how much noise do I need' is an important question I must ask myself. Based on my back-of-an-envelope calculations, it should at least be less than 2 mV RMS, that's an approximate RMS value of the white noise generated by opamps which will be amplifying the signal. Plus there will be some noise received by the sensor itself. So, I guess, anything better than 10 bits should be sufficient for my application. 

Still, the initial question was 'do I get less noise in my ADCs if I split the ground planes or make a single one?'. I wanted to know an estimate answer before I actually manufacture the first iteration of my board. I guess I will just make it one polygon for now.

[T3sl4co1l]

Initial reactions:

Beginners section: "Split ground?"

- If you have to ask, the answer is NO.  Flood both layers and stitch frequently.

Layout: it looks pretty good actually, there's ground fill, there's stitching vias.  Well, some.  Seems not terrible.  Best yet: the signals group together and neck down where they enter the ADC area, well supported by ground plane (not ground surrounding for some reason, but one layer is something).

- So I don't think you're, at least, all THAT beginner.  You may be ready for learning this after all.

So, the thing you're missing, the violation you've made -- is making a loop.  You've gouged out the top layer from the signal bridge down to the bottom edge (between hole and connector), which would be fine if nothing connects around that way, but in fact you've got the, whatever it is, regulated power I'm guessing -- tied in there, along with a ground.  It's also not a perfect slot, as the other power trace (unregulated input?) cuts along the bottom layer, feeding J9, J10 and such.  If those connectors have noisy loads, then the noise will couple into the ground loop (as a crude air core transformer), a fraction of which will go through the ADC area, because the loop forms a shorted turn.

Also, it looks weird having ground ride up alongside that trace on the bottom layer -- it doesn't do anything (in fact, it's stitched with a couple vias at the top and bottom ends), but it's connecting on the top layer anyway so why not flood all of it..?  Also, there are unconnected (by the looks of it) islands, on the left board edge, behind the corner holes, and maybe some other places.  (These can be removed with a polygon setting.)

So, what you want to do is, break that ground bridge, and move the power trace over with the signals, so there is very little current imposed through the ADC area.  If the power line is "dirty", some filtering can be added (maybe a 390R ferrite bead and 0.1uF cap?).

That leaves a secondary consideration, which is that the necked-off ADC ground pour acts as a "paddle" on a wire -- an antenna, and the signal traces are coupling into it.  This is unlikely to be an emissions problem for average-speed digital signals and the size of the board, but it can be an otherwise-easily-overlooked problem when the size is accidentally too large for the signal speed.

It can be a susceptibility problem, even when the signals are relatively slow.  At the resonant frequency, voltage on the antenna "paddle" can be many times higher than the ambient electric field, and the displacement current (carried by the ground, and coupled into the traces, along the neck / bridge section) can be equally large.  Even if that's ambient noise at, say, 1GHz, that can be rectified by input protection diodes, and the resulting "DC" level affects your logic thresholds.  Add some modulation and you've got digital trash.

Three methods address this.
1. Better shielding.  If the signal traces couple into the antenna mode less, then the noise margin is that much higher.

We can introduce shielding by pouring the bottom side copper over the bridge; widening the bridge; interleaving the signals with ground fill / traces; or just shielding the whole thing by putting metal over it.

2. Damping the resonant mode.

This doesn't affect the amount of coupling, but it does reduce the peakiness.  Say it resonates at 1GHz +/- 5%, that's a Q of 10 and a multiplication factor of 10 as well.  Suppose we could dampen that down to a Q of 1 or so instead: then it resonates at 1GHz +/- a lot (a broad, slight peak), and the worst case noise margin is now 10 times better.

Damping can be applied by bridging the resonator with a resistor or R+C.  The voltage on most of the "paddle" is fairly similar, so it would serve to put a chip resistor from ground to ground at the edges of the board, straddling the slot.

Alternately, where the connection necks down, you can wrap that with a ferrite bead.  That's not very practical on a PCB, but is very practical when your signals neck down into a round shape, some sort of... cable, you might say.

3. Get better coupling.  This is basically the same things again, but worded and implemented differently.  Suppose we pick off some of the RF currents flowing through the ground bridge.  Suppose we couple some of that into the signal lines.  We can reduce the interference voltage by keeping the signal-to-ground voltage equal on either side of the bridge.  (Also, this wording suggests simply filtering the signals with respect to ground at the point of use, which is also a fine method when filtering is acceptable.)  This method can be used on the PCB, typically by passing the signals through common mode chokes.  You'd use data-line type chokes, one winding of each being grounded on both sides, and the signal goes through the other winding.  (Common mode chokes also have considerable impedance, further spoiling the antenna mode we're fighting here.  Mind, don't get carried away with it -- at low frequencies, the CMC starts looking like an okay inductor, and you can make an inductor-loaded antenna that way.)  With ground carried through the CMCs, a solid ground bridge is no longer needed (and you would then draw the schematic showing a different ground on the ADC side (GNDA or whatever).  Note: the supply must be choked the same way -- treat it like just another signal.

In short: anywhere you have copper, ask yourself: will this carry current?  Do I want that current?  What happens to the current?  Will it carry currents somewhere I don't want them?

HTH,

Tim

[floobydust]

The ethernet jack shield seems connected to the ground pour, along with the cap maybe C28.
I wouldn't go with that as it ensures the ground pour is noisy with ethernet common-mode hash. In essence, connecting a big antenna to your PCB ground pour.

Instead I use a dedicated small pour (island) connecting to the chassis ground (screw) for the ethernet shield and CM cap.

OP did not say what kind of box is planned. Assuming a metal enclosure, you don't want a ground loop from shield to case, if the circuit ground is connected to shield. I use 5-22nF caps from the big ground-pour to the mounting screws, when there is a metal enclosure to ground without creating DC/LF loops, like for the ADC sensors and their field wiring.

[Sparker]

Seems not terrible.

Thanks, Tim! That's an answer worth if not a textbook, but maybe one of these tutorials by AD/other companies discussing the ground separation topic! 

What I didn't quite get is this (besides the 1 GHz magic, for which I don't have much experience to appreciate all of it yet  ):

break that ground bridge, and move the power trace over with the signals, so there is very little current imposed through the ADC area.

I assume you meant not breaking the bridge, but breaking the ground loop, so that it looks like at the attached picture, right? Or do you mean just pouring everything with the GND polygon (and thus, kind of, 'breaking' the bridge)? I intended to make that ground polygon on the left of the top layer as a separate return path for the analog power supply. Also J10 and J9 will not have any heavy currents run through them.

The ethernet jack shield seems connected to the ground pour, along with the cap maybe C28.

Yes you are right.I have overlooked this problem. I don't quite understand though how it's going to affect my design if I am going to use unshielded Ethernet connectors with unshielded twisted pair. 
As for the case, this PCB will be in an underwater sealed metal tube with internal battery supply mounted on a dielectric platform. I will to connect the negative battery contact to the case. The Ethernet cable will only run for about 10...20 centimeters to another Ethernet switch.

[T3sl4co1l]

What I didn't quite get is this (besides the 1 GHz magic, for which I don't have much experience to appreciate all of it yet  ):

That's simple enough, just at a small enough scale that it ends up pretty high like that.

Consider the board as a single piece of copper.  Ignore the traces that are on it, ignore the functionality it has.  Consider all nets shorted together so it's basically a solid plane of copper.

The neck-down acts as an inductance, and the two full-pour areas act as capacitors (low frequency equivalents).  Thus you get a resonance between two capacitors in series with an inductor.

Given the dimensions, that resonance will come in the ~1GHz range, I would guess.

Frequency here is only a matter of scale.  A larger board might resonate in the 500MHz range, where a handheld FRS radio could interfere.  Or two boards joined by a short cable might resonate in the 200MHz range.  Or with short or long cables attached, 100MHz or less, where commercial broadcast radio, television and other sources would be a problem.

Now consider the board as it is.  There is ground providing such a path, but there are also traces routed in parallel with that bridging inductance, which will couple to it.  That coupling introduces some of the RF from that resonance.  Which means, equivalently: some RF at that frequency, if contained in the signals, can radiate out from that antenna structure; and external interference, if it happens to be strong enough and at an unlucky frequency (near the peak resonance), will couple into the traces.

You can draw an equivalent transformer circuit for this, representing what the signals will see, in terms of, say, a very small capacitor from a nearby noise source.

Well.  Maybe network synthesis is still a rather more advanced topic...

Speaking of cables, the same premise applies there, too: the longer they are, the more noise they can bring in, and they're bringing it right into the middle of the ADC area.  A better layout -- assuming you had the board area to accommodate it -- would have the cables near the slot/bridge, and the ADC stuff off to one side, so the noise currents do not cross the ADC section.  Also, RFI filtering on the analog signals is a must.

These are more considerations for proper commercial (CE approved) products, but you will find that practice very valuable if you go into (or are already!) design of such things.

For the amateur, if you don't mind occasional malfunction, or you are fine dealing with it in other ways (piles of ferrite beads on cables, wrapping the enclosure with tin foil, etc.), you don't need to worry about this.  Or, much of anything, really, just pour that board and route the traces however.  If it's not low noise in the 16+ bits range, I doubt it's going to matter much.

I assume you meant not breaking the bridge, but breaking the ground loop, so that it looks like at the attached picture, right? Or do you mean just pouring everything with the GND polygon (and thus, kind of, 'breaking' the bridge)? I intended to make that ground polygon on the left of the top layer as a separate return path for the analog power supply. Also J10 and J9 will not have any heavy currents run through them.

Perfect!

Hey wait, if those don't carry heavy currents, and you're okay necking down the one trace... why do they need to be fat at all?  Just run a 0.25-0.5 mm trace up there and be done with it.  More space for ground fill!

Yes you are right.I have overlooked this problem. I don't quite understand though how it's going to affect my design if I am going to use unshielded Ethernet connectors with unshielded twisted pair. 
As for the case, this PCB will be in an underwater sealed metal tube with internal battery supply mounted on a dielectric platform. I will to connect the negative battery contact to the case. The Ethernet cable will only run for about 10...20 centimeters to another Ethernet switch.

Oh neat, a submersible project.

Yeah, that's fine to ground anywhere.

Tim

[floobydust]

It looks like the A/D's are exclusively powered off 3V3A. I can't tell where A/D VIO goes, it should run off 3V3D but I see no pcb trace.
I think RF return currents are going to make a mess of a split-plane as you have it.

If you want 16-bit or better performance, there are many things beyond pcb grounding to look after.
Missing any one design element will add noise to the A/D's and scuttle the best intentions.

Quiet rails are important, I don't see much for bulk capacitance or use of ferrite beads, or impedance-matching resistors on SPI to lower reflections.

[Sparker]

Well.  Maybe network synthesis is still a rather more advanced topic...

Allright, I think now I get the explanation!  If I get it right, the equivalent circuit should be something like this (the Paint drawing attached). If I understand correctly, that's also why they use differential I/O in high speed digital circuits, because the differential signals produce opposite coupling into these parasitic inductors.

Speaking of cables, the same premise applies there, too: the longer they are, the more noise they can bring in, and they're bringing it right into the middle of the ADC area.

Do you mean the noise brought by a different level of ground at the other board I'm connecting? Actually this made me thinking, since my ADC is pseudo-differential, should I rather connect the external cable to the ground together with the negative ADC input, or connect the incoming cable's ground to the neg. input without connecting it to the ground?  I guess it would cancel out that imbalanced ground current between the board. FOr now I've put a jumper so that I can figure out what's better later.

floobydust, thanks for your further help with the ADCs!
Currently I am using the following schematic from the datasheet (see the attached picture). 3.3V analog supply is provided by a separate IFX117ME 3.3 regulator. I don't care about absolute reference tolerance for it, so the  power supply as reference is OK for me. The other IFX117ME powers the digital 3.3V bus, which powers the MCU and the Ethernet PHY. What do you think of it?

No, there are no ferrite beads, except for the Ethernet supply. There are also no resistors on the digital lines currently, but if these are so important, I will try to add them. By the way, I can also tweak the slew rate of the I/O of the MCU through its registers to address this issue.

[T3sl4co1l]

Allright, I think now I get the explanation!  If I get it right, the equivalent circuit should be something like this (the Paint drawing attached). If I understand correctly, that's also why they use differential I/O in high speed digital circuits, because the differential signals produce opposite coupling into these parasitic inductors.

Yes!  Precisely! 

Again, the coupling isn't very much, but it is nonzero, and this is how it happens. 

Do you mean the noise brought by a different level of ground at the other board I'm connecting? Actually this made me thinking, since my ADC is pseudo-differential, should I rather connect the external cable to the ground together with the negative ADC input, or connect the incoming cable's ground to the neg. input without connecting it to the ground?  I guess it would cancel out that imbalanced ground current between the board. FOr now I've put a jumper so that I can figure out what's better later.

A differential pair isn't really needed if you use the cable in a differential manner.  Say it's coax (so, shielded to begin with), and isn't carrying much DC power, so the voltage drop along the shield is very small.  The voltage between signal and shield will be consistent along the cable.  Just make sure it's well grounded at both ends, and any (common mode) noise current will flow around and over circuit ground, rather than coupling into the signal.  (Again, we have that transformer action, primarily at the ends where the shield is broken -- and we must ensure it has low enough coupling so the signal stays clean.)

If it's screened multiconductor cable, the screen can be grounded (to enclosure or circuit ground), and the wires sensed differentially.  If unshielded... differential still helps, but you'll probably need filtering to be sure (which is fine if your ADC bandwidth is, say, 10s of kHz tops).

Tim