Not reading in detail here, just dropping comments on the schematic, concerns mentioned, and some of mine:
- Flyback diode is a good idea, and indeed wire inductance can total up some amount here. It should be fairly small (some ~uH; cable inductance goes as about half of \$\mu_0\$ or 0.6 uH/m; can be less if closely paired), so the 1A diode is likely overkill, but that's fine.
- And the local bypass cap goes with that. Likely such a large value isn't needed either, but something is needed, so that's good.
- Oh, at a glance it's not clear if this is one per LED, or many in parallel and this switch is common. If it's more than one, then, well -- I have no idea what a 5Q2364EE5 is, it doesn't turn up anywhere, maybe it's rated enough, maybe not, no idea. I'll assume one each for now.
- C2 is bad: it doesn't do all that much to turn-on speed, and the LC resonance in the gate-source loop likely makes it oscillate in the transition region. A few to tens of ohms in series would damp that.
- The reason it doesn't do much is Cgd is very small on modern MOSFETs. If this were like a IRF540 instead, it'll be more noticeable as far as slowing gate voltage affecting drain voltage speed, but it's less and less effective for this reason. Instead, consider an R+C from D to G, to increase (and stabilize -- the internal capacitance is very nonlinear, dominant at low Vds but almost negligible at high) the Miller effect.
- Likewise, I don't get the speed-up diode on turn-off, that seems to be undoing things half the time. Note that drain swing (in terms of dI/dt or dV/dt) still isn't dictated strictly by that, because you could toss extra capacitance out there for example, which slows the dV/dt. Downside is, that capacitance also stores some energy that the LEDs might continue to glow on (depending on how far it discharges due to line inductance -- which we can't count on if lines are "up to 15m", not consistently long). So you might even want a pull-up resistor or FET to force the LEDs off.
- There's also no short circuit protection, which, meh, maybe that's not too important either -- maybe the 24V supply is limited and the transistor is big enough to brown it out (including all caps in parallel!) or blow the fuse. Maybe total failure in this case is simply an acceptable sequence of events, that can be fine too.
So, the better way to deal with transistor speed, is to return some Cgd, with damping resistance, so that Miller effect dominates the rise and fall; and some LC filtering may still be desirable for dI/dt, or gate dV/dt which will also control drain dI/dt (which is to say, R1 and D1). Filtering can also be added to the output, particularly if enough internal noise remains (say from PWM edges feeding straight through the transistor -- it's a tiny effect, but keep in mind, ~mV matter for EMI). Which might be as simple as a ferrite bead, or a CLC filter section (plus some damping R+C at the output so it doesn't ring).
As for amount, preferably the emissions at the switch should be low enough that the wire length doesn't behave as an antenna. So, 15m, call it 1/4 wave at 60m or 10MHz, so we should be much slower than that -- >>50ns edge rate.
We also can't be too slow, because the ~1kHz PWM needs some range of adjustment; that's a 1000us period, but 10% duty isn't much visual reduction yet only a 50us on-time already. And it takes more like 1% and below to get a significant reduction -- visual response is logarithmic, more or less, so it's quite demanding on PWM dynamic range. So, if we switch as slow as ~1us, that starts to eat into the duty cycle in the single-percent range, and we might want another method instead.
Anyway, somewhere in that range, air on the side of slower switching, for insurance; if we say 500ns, and load current is 1A, then the load will swing 24V in 500ns with a capacitance (Cds) of C = I dt/dV or about 21nF. I'd use not pure C, but an R+C here, maybe 10R + 22nF. That limits peak turn-on current and the resistance makes oscillation less likely.
For the Miller effect network (G-D), this is in ratio to the input resistance, and also assuming more than some minimum load current (if insufficient load current is present, the drain side simply won't rise fast enough to make Miller effect happen). If we say Rin = 100R, and the gain ratio is say 24V/5V, and we effectively have an integrator with Rin = 100R and Cint = Cgd making a ramp from 0...24V in 500ns, then: C ~ 680 to 1000pF should be right. And, at least 10R in series with it to prevent oscillation, but beyond that, this can be tested to see how round of a waveform you get.
These two networks are exclusive, in that the hand-waved derivations above don't account for each other. Probably best is to use both but reduce each of their values by half or so, on the assumption that they will together drop the slew rate / bandwidth by a similar amount. So maybe 10nF + 10R at the drain/load, and 330pF + 10R at drain-gate. And that would be just R1, remove D1 and C2.
And you could still use C2, which could affect some additional rounding-off of edges, but don't place it directly on the gate, either put some resistance in series (ca. 10R) as mentioned, or you could divide R1 in half say, and put it there -- in that case it acts to filter the input, rounding off the logic edges. Some nF would still be a fine value.
Or increase R1 (or its respective splittings) and decrease C2 and the Miller (G-D) C, and increase Miller R, proportionally. Probably C2 on the order of Ciss is fine, so, whatever that is for the transistor.
Tim
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