Ok, so a while ago someone on here suggested to me a trick (sorry, can't remember who, but thank you, it looks like it can be a very useful trick to me) for amplification of signals too fast for the op amps I had to hand by using a 74HCU04 (or other UNBUFFERED NOT gate chips) in a linear mode.
This involves coupling a capacitor from the signal source to one end of an input resistor, the other end of the input resistor goes to the NOT gate's input, a feedback resistor then runs from the gate's input pin to its output, and the output can then, either with capacitive coupling*, or directly*, be used to provide higher voltage signals to further circuit elements.
*some descriptions seem to show the capacitor on the output, others don't I certainly didn't seem much effect when having it there versus replaced by just a wire, both when the amplifier's final output was driving just an o-scope probe (10Mohm, <12pF), and when it was driving in to a 1K resistor to ground as well as the scope probe. Is there a reason they show it, if one is driving a second stage of CMOS inverter amplification then surely one only needs the coupling capacitor input one would already fit it with if it were acting independently, no need for an extra coupling cap?
National Semiconductor's AN-88 app note covers this concept "CMOS Linear Applications" briefly.
I've been giving it a go and found some odd things and wanted to understand a bit more, but don't know where I can get further info, because AN-88 doesn't say a vast amount (even so much as not giving the equations and full captions you'd expect for its figures), and google searching didn't find me that many full answers, just discussions. This
https://wiki.analog.com/university/courses/electronics/electronics-lab-20 also covers some stuff, but not enough either.
I had thought the ratio of the input and feedback resistors will equal the gain, roughly, but I'm finding things very diferent. For a 3MHz sine signal input(500mV peak to peak) with a 5V and ground power supply for the inverter chip I'm needing resistor ratios of 10s to get gains of 3. I'm also finding things don't seem to depend solely on the ratio, a larger pair of resistors with the same ratio doesn'tgive the same gain, not even close, as a smaller pair. A 1K input and 10K feedback gives a gain of around 3, whereas a 10K input and 100K feedback gives a gain less than 1.
Is there a clear equation governing the gain of a CMOS inverter amplifier, ignoring circumstances where one is trying to gain something to the extent it would come very close to the rail?
Is there some sort of "slew rate" like thing going on here, perhaps controlled by the absolute sizes of the resistances rather than their ratios, where gain is limited for a signal at a particular speed?
Then when I stacked up two CMOS inverter amplifiers with one feeding the input of the next, keeping the coupling capacitors an input resistors so each alone was just the same circuit as a single one acting alone would be, I got a gain from the pair much greater than the product of the gains either had given when used alone.
Are they interacting with each other in some manner, or does the output of one provide some input impedance effect to the next stage despite having an input resistor present?
And I had expected that when the input and feedback resistors were equal I'd get a gain of 1, but instead I found a gain much less than 1, again varying with how big the resistors actually were. Yet when putting two such amplifiers in sequence, the first with a large enough ratio to give a gain and the second with a 1:1 ratio, the final output was nonetheless larger than the gain of just the first stage alone.
Trying to work out empirical equations for whatever is going on would require varying an awful lot of independent parameters it seems, resistance sizes as well as ratios, amplifiers in sequence and alone...
Another thing I found was that within a single chip, I could run two amplifier stage just fine, but if I tried three amplifier stages then I got a much higher frequency signal(15 to 20MHz maybe) superimposed on the waveform, and when the input signal was weak and one would expect the output to be sitting at close to 2.5V and nearly flat, I instead got this high frequency waveform becoming dominant.
I'm also a bit unsure about the maximum number of elements in the hex chip one should use, a single gate acting in this manner, with the others all grounded on their inputs, has the chip comsuming about 12mA. There is an abs max figure given in most 74HCU04 datasheets of 50mA for the whole chip, and 25mA per channel, but no recommend long term operating maximum. Does this mean I'm ok to run up to 4 gates in this fashion, 4x12<50, or is there a further percentage by which I should try to work below the abs-max current draw? The chip (DIP in breadboard testing, SOIC in my final application) doesn't have any obvious pad for heatsinking if I ought to do that, but I could make the ground and power planes/traces near the chip's suppply pins big with lots of vias if that would be wise?
Can anyone point to resources that give the full details on how to make use of this "Unbuffered CMOS NOT GATE as amplifier" trick, particularly an equation to let one select the most appropriate resistors for a desired gain rather than having to trial-and-error it.
Thank you