| Electronics > Beginners |
| How to determine if PLL 4046 is locked? |
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| Benta:
It might be in lock. Reread my reply #6. The PFD I will only provide a frequency lock, not a phase lock. If the signal at pin 1 is a stable square wave, your loop is frequency locked as expected. |
| ZeroResistance:
--- Quote from: Benta on August 11, 2018, 06:01:39 pm ---It might be in lock. Reread my reply #6. The PFD I will only provide a frequency lock, not a phase lock. If the signal at pin 1 is a stable square wave, your loop is frequency locked as expected. --- End quote --- In the datasheet "Pin 1" is only referred to during Phase Comparator II operation, does it apply to Phase Comparator 1 also? |
| Benta:
--- Quote from: ZeroResistance on August 11, 2018, 06:28:46 pm --- --- Quote from: Benta on August 11, 2018, 06:01:39 pm ---It might be in lock. Reread my reply #6. The PFD I will only provide a frequency lock, not a phase lock. If the signal at pin 1 is a stable square wave, your loop is frequency locked as expected. --- End quote --- In the datasheet "Pin 1" is only referred to during Phase Comparator II operation, does it apply to Phase Comparator 1 also? --- End quote --- Yes, insofar as the two PFDs are in parallel, and PFD II is forced to run out of lock when using PFD I, the pin 1 output indirectly also applies to PFD I. |
| ZeroResistance:
Okay so I'm adding some more waveforms here. First waveform shows relation between VCO out and Signal In. Second waveform shows the original resonant capacitor waveform that i wan to lock onto and Signal In (Derived from the resonant capacitor) My question is Signal In required to be a square wave of CMOS levels. Or is the signal shown in the waveform a valid signal for the PLL to operate? |
| T3sl4co1l:
You claimed "sine wave", but the output will never be a sine wave. What are you really trying to do here? :) If you have an output coupling network (seems likely, for dielectric heating?), put that in the loop! FYI, because this circuit is self driven, it's never "out of lock", though you might be unhappy with how it is locked (i.e., out of phase, or unstable control loop). It should be pretty easy to get it to behave. Mind that you will need the two phase signals of interest: presumably, output voltage and resonant current. You can't use the oscillator output directly due to phase shift through the driver and output chain. Mind also that the kind of 4046 matters. The original CD4046 is apparently the best, albeit probably too slow for this. The 74HC4046 was a chintzy hackjob of a clone, with deadband in its type II detector, and a much worse (nonlinear, drifty) oscillator. There are also "improved" versions (HC7046 and I think 9046?) that still aren't as good as the original (in all aspects but speed), and have another PFD type available. (Disclaimer: this is what I've heard; I have had few PLL applications myself, so this is not first hand experience, let alone with data to back it up.) You may well be better served with a semi-discrete solution: a VCO, driver, PFD and error amp, all separate components (probably still ICs, or gates or whatever, just not a single-chip solution). That's how I design induction heaters (same thing, inductive rather than capacitive load). Could also potentially use a frequency multiplier to get higher frequencies from a lower frequency osc/PLL, if that's a problem. Tim |
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