Electronics > Beginners

How to determine if PLL 4046 is locked?

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ZeroResistance:

--- Quote from: T3sl4co1l on August 11, 2018, 07:22:44 pm ---You claimed "sine wave", but the output will never be a sine wave.  What are you really trying to do here? :)

--- End quote ---

I do see a half rectified kind of sine wave across the resonant capacitor.


--- Quote ---If you have an output coupling network (seems likely, for dielectric heating?), put that in the loop!

--- End quote ---
i don't have any coupling network yet, i was planning to connect 2 parallel plates across the resonant capacitor and then put some material between the parallel plates to be heated.


--- Quote ---FYI, because this circuit is self driven, it's never "out of lock", though you might be unhappy with how it is locked (i.e., out of phase, or unstable control loop).

--- End quote ---
I'm sorry I didn't get this. When I load the material into the output plates the resonant capacitor would change and so would the frequency. The would change the switching of the mosfets out of their zero voltage / zero voltage switching. I want to achieve zvs / zcs even though the capacitor and frequency changes.
It should be pretty easy to get it to behave.  Mind that you will need the two phase signals of interest: presumably, output voltage and resonant current.  You can't use the oscillator output directly due to phase shift through the driver and output chain.


--- Quote ---Mind also that the kind of 4046 matters.  The original CD4046 is apparently the best, albeit probably too slow for this.  The 74HC4046 was a chintzy hackjob of a clone, with deadband in its type II detector, and a much worse (nonlinear, drifty) oscillator.  There are also "improved" versions (HC7046 and I think 9046?) that still aren't as good as the original (in all aspects but speed), and have another PFD type available.  (Disclaimer: this is what I've heard; I have had few PLL applications myself, so this is not first hand experience, let alone with data to back it up.)

--- End quote ---
I am currently using an HCF4046 from ST, altough it is not suitable for this application because I need a higher frequency preferably 3 to 5Mhz.


--- Quote ---You may well be better served with a semi-discrete solution: a VCO, driver, PFD and error amp, all separate components (probably still ICs, or gates or whatever, just not a single-chip solution).  That's how I design induction heaters (same thing, inductive rather than capacitive load).  Could also potentially use a frequency multiplier to get higher frequencies from a lower frequency osc/PLL, if that's a problem.

Tim

--- End quote ---

Good Idea regarding the frequency multiplier..
So If I still want to continue using this chip for say 5Mhz would I need both a multiplier (for feeding to the mosfet driver) and divider for feed back into the signal input?

iMo:

--- Quote from: Benta on August 11, 2018, 06:53:17 pm ---
--- Quote from: ZeroResistance on August 11, 2018, 06:28:46 pm ---
--- Quote from: Benta on August 11, 2018, 06:01:39 pm ---It might be in lock. Reread my reply #6. The PFD I will only provide a frequency lock, not a phase lock. If the signal at pin 1 is a stable square wave, your loop is frequency locked as expected.

--- End quote ---
In the datasheet "Pin 1" is only referred to during Phase Comparator II operation, does it apply to Phase Comparator 1 also?

--- End quote ---

Yes, insofar as the two PFDs are in parallel, and PFD II is forced to run out of lock when using PFD I, the pin 1 output indirectly also applies to PFD I.

--- End quote ---
The PIN1 "lock" indication will not work with PFD1 (the simple XOR). The XOR "continuosly wobbles" around the "lock" position, thus the PIN1 shows a square wave.
The PFDII when "locked" stops pumping the current into/from the filter, thus you get PIN1 high when the phase is zero (plus minus dead time for some 4046 variants).


--- Quote ---Whats the reason for the "1.855-1.865V the PLL is considered "locked""? Do you use 15V supply voltage?
--- End quote ---
It was a "for example". The voltage at which the XOR PD is considered to be "locked" depends on many factors. It could be any voltage from almost 0V to almost 15V in your case.

T3sl4co1l:

--- Quote from: ZeroResistance on August 11, 2018, 07:48:07 pm ---I'm sorry I didn't get this. When I load the material into the output plates the resonant capacitor would change and so would the frequency. The would change the switching of the mosfets out of their zero voltage / zero voltage switching. I want to achieve zvs / zcs even though the capacitor and frequency changes.
It should be pretty easy to get it to behave.  Mind that you will need the two phase signals of interest: presumably, output voltage and resonant current.  You can't use the oscillator output directly due to phase shift through the driver and output chain.

--- End quote ---

Yeah, you might not like what lock condition it's in, but it's never not in a lock condition.  In Diff Eq, this is a non-homogeneous system.  When the system is linear (as an RLC network is), the steady-state solutions are always at the driven frequency (assuming the "driver" is a periodic signal, of course).

In simpler terms: no matter what frequency you're driving at, the network is always doing whatever it's doing, at that same frequency.  There is no locking to be done*, because it's always locked on frequency.

*In the sense that the phase might go outside of (-pi, pi] (in terms of total phase, not modulo phase).

This makes PLLing a resonant network much easier than the general case (typically, a PLL locking to a completely arbitrary and separate signal, like for radio).  So that helps!

PLLing a class E stage (with no output network) is even easier still, because it's not resonant at all, as such.  It's quasi-resonant.  There's a half-sine* hump, then the voltage goes back to its initial state, and current goes back to ramping up.  The ramp duration is variable.  To a certain extent, you can drive over a wide frequency range, and get output power proportional to frequency (though this is probably prohibitive because of peak current and voltage demands on the switch).

*It's still not actually a sine part, but a segment of a decaying sinusoid.  And if we include real components, not even that, because MOSFET Coss is nonlinear, so the zero crossings are rather slower (more Coss at lower Vds) than expected.

Be very careful talking about precise things like waveforms!  If you say "sine wave", I fully expect something very tightly defined in the frequency domain: one spectral line, no distortion, no sidebands (maybe a DC offset, but strictly speaking, no).  As soon as you have "sine wave BUT", the spectrum goes out the window, and it simply doesn't have the properties of a sine wave, and should not be called that. :)

Tim

iMo:
While trying to understand your schematics (I have to rotate my notebook upside down) - what the 10k pot-trimer actually does?
I think it cannot be wired that way..
Could you describe what the system shall actually do?

Benta:

--- Quote from: ZeroResistance on August 11, 2018, 06:57:00 pm ---
My question is Signal In required to be a square wave of CMOS levels. Or is the signal shown in the waveform a valid signal for the PLL to operate?

--- End quote ---

Your first plot shows exactly what is to be expected from using PD I. A locked signal with appr. 90 degrees shift. The 4046 has an input amplifier, your input signal is perfectly OK. It works as it should.
And No, the XOR does not "continually wobble", no idea where that came from.

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