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How to drive PN FET pair in high voltage H-bridge
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IvanBayan:
Hello.
I trying to build H-bridge based on PN FET pair, I've found a lot of schemes for voltages below Vgs break voltage, but how to drive FETs if voltage above Vgs limit?
I found scheme below:
But don't undestand how it works, at the end right FET pair controlled by signal with 2*Vdd amplitude?
Here is another solution which I found:
If I undestand correctly, gate current will be limited by zener maximum current?
Is there a well-known scheme for H-bridge which based on PN pair?
Thank you.
PS
I know about solutions which based on N FETs and bootstrap capacitor, but them need PWM to keep upper N FET open.
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