Converting "high" frequency 5V to 3.3V

[Macka]

Hi guys,

Well, as the title says, I'm wanting to convert a signal 0 - ~800kHz from 5V to 3.3V for input into an ICP pin and a D-Flip-flop. I'm looking at using a BSS138 in the configuration shown here: https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf (I'm not using this sparkfun part and I don't need bidirectional support).

The 5V signal is coming from an HEF4069UB hex inverter, it then needs to be converted to 3.3V. The 3.3V signal will be split and fed into an MC74AC74D D-Flip-flop and a SAM3SD8 MCU.

As I understand it, there are 2 conditions required for a MOSFET to work in this scenario:
1) The output needs to be open drain
2) The RC constant of the MOSFET must be such that the rise time is fast enough on the 3.3V side

I can see the hex inverter has a totem-pole configuration (which I guess is to be expected), so I know it will push and pull the output signal. My understanding is this is equivalent to an open drain config and I should be able to omit the HV pull up resistor, R4, from the MOSFET.

Now, if I understand the conversion correctly, a high output from the hex inverter will result in no flow through the MOSFET and 3.3V on the LV side. A low output from the hex inverter will put the MOSFET's internal diode in forward bias, which will pull the LV side low, as long as R3 is large enough.

Could someone please confirm if this is correct?

Could someone please confirm if the RC constant is an issue with the one way conversion or does it only apply when level shifting in both directions? My suspicion is it doesn't apply since we are only relying on the internal diode and not the MOSFET.

Could this be achieved with a single diode instead?

I don't know what I don't know, so any help is appreciated.

Thanks.

[danadak]

One way to consider is simply use a series R between 5V logic and 3.3. The
3.3V logic input parasitic diode (IPD) will clamp the high level to 3.3 V + 1 diode drop.
The R must be large enough to minimize IPD current and to prevent parasitic SCR
trigger which can be catastrophic. But not so large that leakage current starts to
effect noise margin.

https://www.fairchildsemi.com/application-notes/AN/AN-339.pdf

Or use a simple transistor, feed base thru an R, R in collector to 5V, collector to
downstream logic. Note add R from base to ground to prevent turn on due to leakage
when upstream logic is tri stated.

This approach has the undesirable effect of altering effective duty cycle for the load
parts, but the D F-F will return that to 50%.

Alternatively use single gate logic level translator, Fairchild, OnSemi.....

http://www.ti.com/lit/ds/symlink/sn74lv1t34.pdf



Regards, Dana.

[rob77]

Hi guys,

Well, as the title says, I'm wanting to convert a signal 0 - ~800kHz from 5V to 3.3V for input into an ICP pin and a D-Flip-flop. I'm looking at using a BSS138 in the configuration shown here: https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf (I'm not using this sparkfun part and I don't need bidirectional support).

The 5V signal is coming from an HEF4069UB hex inverter, it then needs to be converted to 3.3V. The 3.3V signal will be split and fed into an MC74AC74D D-Flip-flop and a SAM3SD8 MCU.

As I understand it, there are 2 conditions required for a MOSFET to work in this scenario:
1) The output needs to be open drain
2) The RC constant of the MOSFET must be such that the rise time is fast enough on the 3.3V side

1) NO , any output works . if it's open drain/colector then it uses the 10K pull-up and if it's not then it's the 10k pull-up in paralel with whatever the output circuit has.
2) NO , the gate is directly connected to low supply without a series resistor (in your case directly to 3.3V) so it will switch really fast. 800kHz is no speed, just relax

[pigrew]

Could someone please confirm if the RC constant is an issue with the one way conversion or does it only apply when level shifting in both directions? My suspicion is it doesn't apply since we are only relying on the internal diode and not the MOSFET.

Could this be achieved with a single diode instead?

Thanks.

You can omit the resistor on the input side, since the source is push-pull.

However, you still would need a pull-up resistor on the output. The way the circuit works is that if one side is low, it pulls the other side low. On the other hand, if the input is high, it turns off the transistor, and the two sides are isolated from each other (hence the requirement for the pull-up resistor).

You still have to worry about RC delays when the device is transitioning from low to high. The R would be the pull-up resistor value and the C would be the input capacitance of your IC, capacitance of your MOSFET (C_oss? I forget exactly which one it is....), and board parasitics.

You should try simulating the circuit using spice (LT-Spice, for example) to see how quickly it responds. The flip-flop's input is around 4.5 pF, and you can check your microcontroller's datasheet for its input (likely in the 5 to 20 pF range).

If you need something faster, you could reduce the pull-up resistor value, though this will use more power.

You couldn't directly use a pair of diodes in series between the chips because that wouldn't let the source pull down the load. You could use two diodes with a pull-down resistor, though this also runs into RC delay issues.

One good (wastes a little power) solution would be to use a voltage divider to divide the input down to 3.3 V.

If you care about power consumption, you need a CMOS inverter. One example would be the 74LVT04, where you'd use two inverters in series (so that your signal isn't inverted). Don't forget to ground all the unused inputs. If it's OK to invert the signal, you could use the SN74LV1T04, which only contains a single inverter.

[Macka]

One way to consider is simply use a series R between 5V logic and 3.3. The
3.3V logic input parasitic diode (IPD) will clamp the high level to 3.3 V + 1 diode drop.
The R must be large enough to minimize IPD current and to prevent parasitic SCR
trigger which can be catastrophic. But not so large that leakage current starts to
effect noise margin.

https://www.fairchildsemi.com/application-notes/AN/AN-339.pdf

Ahh, I have seen this trick before, however the R values were given. In my case, the MC74AC74D has an I_Latch-up of +/-100mA  above Vcc and below Gnd at 87°C
So I should calculate the resistor as follows:
(5-3.3)/R <100 mA
1.7/R < 100 mA
1.7/100 mA < R
R > 17 Ohm
I could select , say, a 20 Ohm +/-5% >= 0.2 W resistor, which, worst case would give me 19 Ohms and I_gate would be 89 mA

How do I find the upper end of acceptable size to avoid noise margin issues? The data sheet says the minimum high level input voltage is 2.1V @Vcc=3.0V and 3.15V @Vcc=4.5V, extrapolating, I need a minimum voltage of 2.31V, general guidelines say 2.7V for 3.3V CMOS, so I think I'll stick to that for a safety margin.
Data sheet specifies a maximum leakage current I_IN of +1.0 µA
I_min*R = 2.7V
1.0µA * R = 2.7V
R=2.7V/1.0µA
R = 2.7 MOhm

So if my calculations are correct for the D-F-F to work correctly, I need to select a a resistor between 20 Ohms and 2.5 MOhms +/-5% tolerance and >=0.2W

With the SAM3SD8, the data sheet does not specify a latch-up current - not sure what to do there?, but it does specify minimum high level input voltage = 0.7 * V_DDIO, which would make V_IH=2.31V. The max input leakage current is 18 nA.

Without knowing the latch-up current for the MCU, if I selected a 100kOhm resistor I'd have a current of 17µA, which is greater than the combined input leakage currents and (presumably) less than the latch-up current.

Does that seem right?

2) NO , the gate is directly connected to low supply without a series resistor (in your case directly to 3.3V) so it will switch really fast. 800kHz is no speed, just relax

Does the RC come into play when level shifting from 3.3V to 5V? I've seen one post saying this method is no good for >400kHz (but that may apply only to shifting up)

[pigrew]

Without knowing the latch-up current for the MCU, if I selected a 100kOhm resistor I'd have a current of 17µA, which is greater than the combined input leakage currents and (presumably) less than the latch-up current.

Does that seem right?

I didn't check the math, but the numbers seem reasonable.

You still need to worry about RC delays. If you use 100k series, and have a load of 25pF, that's a f_3dB frequency of 80 kHz, and you wouldn't want to run any digital signal more than 1/5 of that... so you'd be limited to perhaps 20 kHz digital signals.

[Macka]

You can omit the resistor on the input side, since the source is push-pull.

However, you still would need a pull-up resistor on the output. The way the circuit works is that if one side is low, it pulls the other side low. On the other hand, if the input is high, it turns off the transistor, and the two sides are isolated from each other (hence the requirement for the pull-up resistor).

You still have to worry about RC delays when the device is transitioning from low to high. The R would be the pull-up resistor value and the C would be the input capacitance of your IC, capacitance of your MOSFET (C_oss? I forget exactly which one it is....), and board parasitics.

You should try simulating the circuit using spice (LT-Spice, for example) to see how quickly it responds. The flip-flop's input is around 4.5 pF, and you can check your microcontroller's datasheet for its input (likely in the 5 to 20 pF range).

If you need something faster, you could reduce the pull-up resistor value, though this will use more power.

You couldn't directly use a pair of diodes in series between the chips because that wouldn't let the source pull down the load. You could use two diodes with a pull-down resistor, though this also runs into RC delay issues.

One good (wastes a little power) solution would be to use a voltage divider to divide the input down to 3.3 V.

If you care about power consumption, you need a CMOS inverter. One example would be the 74LVT04, where you'd use two inverters in series (so that your signal isn't inverted). Don't forget to ground all the unused inputs. If it's OK to invert the signal, you could use the SN74LV1T04, which only contains a single inverter.

C_OSS = 7 pF @ 1MHz, V_DS = 10V and V_GS = 0V
C_F-F = 4.5 pF
microcontroller capacitance is not supplied, assume 20 pF
PCB capacitance ~3.24 pF based on existing design, but is unlikely to change significantly

C_tot = 34.74 pF
R = 10 kOhm
Tau = 3.4E-07 s
however, Tau is only 63% charge, which is below the threshold, 2*Tau is going to be well above the trigger threshold

f_MAX=1/(2*Tau) = 1/6.894e-7 = 1.45 MHz

I'll have to see if I can find a SPICE app to test it, but my calculations look like it's going to be ok, do you agree?

Without knowing the latch-up current for the MCU, if I selected a 100kOhm resistor I'd have a current of 17µA, which is greater than the combined input leakage currents and (presumably) less than the latch-up current.

Does that seem right?

I didn't check the math, but the numbers seem reasonable.

You still need to worry about RC delays. If you use 100k series, and have a load of 25pF, that's a f_3dB frequency of 80 kHz, and you wouldn't want to run any digital signal more than 1/5 of that... so you'd be limited to perhaps 20 kHz digital signals.

Ok, so maybe I have made a mistake in the above calculation, or there's a gap in my knowledge, where does the f_3dB come from?

EDIT:
oh, ok, you're talking about 100k ohm resistor in series without MOSFET, which would make it:
C_F-F = 4.5 pF
microcontroller capacitance is not supplied, assume 20 pF
PCB capacitance ~3.24 pF based on existing design, but is unlikely to change significantly

C_tot = 27.74 pF
R = 100 kOhm
Tau = 2.774E-6 s = 2.77µs
f_MAX=1/(2*Tau) = 180kHz  so too slow.

EDIT 2:
Ok, so if I lower the series resistance to 1kOhm I'd have a frequency of 18MHz, divide by 5 and I can run up to 3.6MHz with a maximum current of 1.7 mA? I'm not so sure I've calculated this correctly.

[pigrew]

I'll look at the math tomorrow.

I'll still a little bit wary of relying on the ESD diodes, though it should work. It'll likely end up operating with the input voltage above the suggested maximum which could potentially cause reliability issues because of Vgs being to high.

I'd still suggest using a simple voltage divider, perhaps a 2k and 3.3k resistor, to divide down the voltage.

Or, add a 5-volt tolerant IC to do the translation, like the 74LVT04.

[Zero999]

If you find it difficult to get a resistor value high enough to limit the current but low enough to give sufficient speed, you can put the resistor in parallel with a capacitor, to bypass it at AC. The value of the capacitor can be selected, to form a capacitive voltage divider with the logic input, so the ESD diode never conducts due to the transient current, only due to the current through the resistor.

https://en.wikipedia.org/wiki/Voltage_divider#Capacitive_divider

For example:
V_IN = 5V
V_OUT = 3.3V
C_OUT = 6pF
C = 6×3.3/(5-3.3) = 11.65pF

The resistor can then be something high like 100k to 1M, with a 12pF capacitor in parallel to pass the AC.

[Ian.M]

Passing current through the ESD diodes of a complex device when they are not specified to carry current in normal operation is always risky.  Substrate charge injection can cause thresholds to shift and also cause on-chip analog circuits and oscillators to misbehave.

A cheap safe high speed option for unidirectional downwards level translation is a potential divider,with a few pF of speedup capacitance across the top resistor to get squarer edges. However determining the capacitive load to calculate the optimum speedup capacitance is difficult.  33K lower, 15K upper would probably be a good place to start, with half the expected load capacitance across the 15K resistor.  As the source impedance of the divider is several orders of magnitude higher than a normal gate output, locate it as close as possible to the gate(s) its driving and keep tracks on the load side short and away from fast-switching signals.

If you need a micropower option, use a 3.3V gate with 5V tolerant inputs, or a dedicated level translating gate.

[danadak]

The calculation of the series R is more complex because you are not
driving it with a V source, rather a current limited PMOS driver in
output of the inverter. And your calculation would cause a lot of un-
necessary Pdiss in the circuit. Additionally as stated previously you
start to get source bulk effects on device thresholds which shift the
trip point of logic wih a lot of current flow. And the Pdiss in package
and Tjmax have to be considered.

A number of these considerations discussed here - http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

So start by calculating R to meet minimum logic in riseime limits.

In his consider margin of calculation, device to device variation
quite large in standard cmos logic. Eg. Cin is usually stated as typical,
use 50% variation as a criteria.

I think you will find K ohm range series R will suffice, but do the spice
sim to evaluate.



Regards, Dana.