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Electronics => Beginners => Topic started by: ommsiva on June 13, 2026, 04:51:20 pm
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Dear All,
For more than four years, I have been trying to build an SMPS-based regulated power supply. As usual, I started with the TL494 datasheet and used one of its reference designs. My goal is to design a buck converter with Constant Current (CC) and Constant Voltage (CV) modes.
I have a 24 V, 10 A transformer. By replacing R1 (1 kΩ) with a variable resistor, I am able to adjust the current limit from nearly 0 A up to 10 A. However, I am unsure how to make the output voltage adjustable.
The voltage error amplifier appears to be configured in an inverting configuration. I noticed that there is a 51 kΩ resistor and a 510 Ω resistor, and that the inverting input receives approximately 2.5 V from a voltage divider connected to the 5 V reference. On the other hand, the non-inverting input samples the output voltage through another resistor divider with equal resistor values.
I have the following questions:
1) Is the voltage error amplifier configured as a non-inverting or an inverting amplifier? Why is there a voltage divider connected to the 5 V reference that generates 2.5 V and feeds the inverting input? What is the purpose of the 51 kΩ feedback resistor in this configuration?
2)How can I modify this circuit to make the output voltage adjustable from the minimum value up to 30 V while retaining the CC/CV functionality?
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Here are a couple of ideas I found for adding voltage control...
https://320volt.com/en/adjustable-switch-mode-power-supply-0-25v-0-5a-tl494/ (https://320volt.com/en/adjustable-switch-mode-power-supply-0-25v-0-5a-tl494/)
Basically 0 to 5V is fed via the 10K pot P2 through R20 into pin 2 with a feedback network consisting of R15, R16 and C14.
https://www.deeptronic.com/electronic-circuit-design/programmable-1-30v-lab-power-suppl/ (https://www.deeptronic.com/electronic-circuit-design/programmable-1-30v-lab-power-suppl/)
This is closer to the original TI design. A PWM signal is fed into node P.2 which is then smoothed out by R12, R13, C10 and U2. You could also just feed a op-amp buffered 0-5V signal into R14.
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I'm surprised by the TL094 circuit also, in real life I'd be afraid to tie the output of 2 op-amps together. That 51k feedback resistor is tied to pin 2, so that will be the feedback for this as a composite amplifier.
The upper op-amp seems to me to have positive feedback, from sensing the current, and the more the current sense voltage is over the Vref divider, the higher that op-amp would go. But I guess once the lower op-amp is accounted for, it will keep the current from increasing.
Yeah this is another composite op-amp circuit I need to try. I'm already on a few side-quests, for trying to calculate the ones in my old Keithley 616 Electrometer
Do you know anything about feedback systems and node equations, etc ? I'd start with a simpler output section, just some other BJT or 2, tied to the output of the op-amps, and then either try the node equations and use the definitions for op-amps, and get an output that way.
Or open the loop somewhere, find the open loop gain, and then use the feedback equation and just find the closed loop gain that way.
But I'd probably run into trouble somewhere, hence the side-quests, at least for trying to calculating it the longer ways I try sometimes.
And also, set your desired output, and work back through the BJT's, and see what's needed for the DC operating point, then I'd start adding the op-amps into it
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I'm surprised by the TL094 circuit also, in real life I'd be afraid to tie the output of 2 op-amps together.
If it helps to assuage your anxiety, they are connected through diodes - see page 10 of the datasheet.
https://www.ti.com/lit/ds/symlink/tl494.pdf (https://www.ti.com/lit/ds/symlink/tl494.pdf)
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Dear sir,
I cant know how to start the analysis for this circuit and understand the operation
https://320volt.com/en/adjustable-switch-mode-power-supply-0-25v-0-5a-tl494/
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Dear sir,
I cant know how to start the analysis for this circuit and understand the operation
https://320volt.com/en/adjustable-switch-mode-power-supply-0-25v-0-5a-tl494/
Error amplifier 1 is used for voltage regulation (TL494 pin 1 & 2).
Error amplifier 2 is used for current regulation (TL494 pin 15 & 16).
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I'm surprised by the TL094 circuit also, in real life I'd be afraid to tie the output of 2 op-amps together.
If it helps to assuage your anxiety, they are connected through diodes - see page 10 of the datasheet.
Texas Instruments published an application node (1) which includes internal details of the TL494. The diodes are actually a pair of NPN followers with their emitter outputs tied together
https://www.ti.com/lit/an/slva001e/slva001e.pdf?ts=1781519918597 (https://www.ti.com/lit/an/slva001e/slva001e.pdf?ts=1781519918597)
It also includes design details of the example circuit. The feedback resistor is used to limit the error amplifier gain to 101 to improve stability.
I am disappointed that the TL494 uses operational amplifiers instead of operational transconductance amplifiers. OTAs are common in other switching regulator ICs and much more versatile.
(1) There are several typos in this application note.
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The TL494 TI App note has an error in Fig 9 the inverting input is not an npn but a pnp.
Best
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1) Is the voltage error amplifier configured as a non-inverting or an inverting amplifier? Why is there a voltage divider connected to the 5 V reference that generates 2.5 V and feeds the inverting input? What is the purpose of the 51 kΩ feedback resistor in this configuration?
Error amplifiers are non-inverting amplifiers because the PWM modulator "inverts" (gives a smaller duty cycle for higher input voltages).
[attach=1]
The division of the reference voltage is a designer's decision; it is not necessary. Error amplifiers have a wide range of common mode voltages from –0.3V to Vcc –2V, which does not impose significant limitations on the design of feedback circuits. In the case of voltage regulation loops, two dividers, are often used. One divides the output voltage, the other the reference voltage. Changing any resistor changes the voltage. Inserting a potentiometer in certain configurations limits the range of regulation or causes the characteristic to be nonlinear; I avoid such solutions. If you eliminate the problematic ones, only one will remain - the regulation between Vref and the (-) of the amplifier.
For more than four years, I have been trying to build an SMPS-based regulated power supply. As usual, I started with the TL494 datasheet and used one of its reference designs. My goal is to design a buck converter with Constant Current (CC) and Constant Voltage (CV) modes.
Designing a power supply is not something that can be described in a single short post. The answer to your questions is not difficult, but time-consuming. That's why people don't provide satisfactory solutions in your topics.
Even if you get all the answers and determine the resistor values, it won't be the end. The next stage will be 10 times more difficult - adjusting the frequency compensation, which means ensuring the stable operation of the power supply so that it doesn't oscillate. In amateur projects, this is notoriously underdeveloped because it requires higher mathematics. That's why the elements attached to pin 3 are usually a random mix from other schematics or nothing at all.
You wrote that you are a student. What are you studying? Do you know complex analysis, the Laplace transform, Bode plots? Would you be able to understand such an article and adapt the solution from it to your project?
https://web.cecs.pdx.edu/~tymerski/chap1.pdf
Four years is a very long time, you could have learned a lot. Since you can't rely on the forum at this level, have you tried to learn on your own? Have you read any books on electronic circuits or SMPS design?
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Hi Sir,
Thank you for your reply.
1) I could not understand the statement:
"If you eliminate the problematic ones, only one will remain - the regulation between Vref and the (-) of the amplifier."
Could you please explain what you mean by this? Which "problematic ones" are you referring to, and how does the regulation occur between Vref and the inverting input of the error amplifier?
2) Regarding your question about learning:
I am an Electronics and Communication Engineer and currently work as a Marketing Executive. However, I am passionate about electronics and want to understand circuit analysis and SMPS design in depth. I regularly study datasheets, application notes, and circuit designs, but I still struggle with some control-loop and feedback concepts. Therefore, I would appreciate any guidance or recommendations for books and learning resources on SMPS design.
Thank you for your time and assistance.
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I regularly study datasheets, application notes, and circuit designs, but I still struggle with some control-loop and feedback concepts. Therefore, I would appreciate any guidance or recommendations for books and learning resources on SMPS design.
With your lack of experience you will struggle to learn theory from datasheets, application notes and circuit designs. Four years with zero progress is testament to that.
To learn theory at your low experience, you need to study university engineering textbooks, not datasheets.
You can learn from simulation as well, but your approach to simulation is also incorrect. Do not simulate the entire power supply, only simulate a single functional block. Unfortunately at your low experience, it appears you are unable to identify functional blocks, and as such, you will not be able to learn anything from simulation either.
Put simply, you need to learn to walk before you run. Over the last four years, you always try to run, and that is your real problem.
My guidance is to build incremental basic small linear power supplies to learn about functional blocks and feedback.
1) fixed voltage 12V @ 1A. This is almost trivial for seasoned engineers using just a 7812 regulator, but for you, this may be too difficult.
2) fixed voltage 12V @ 4A. Use a 7812 regulator and pass transistors.
3) adjustable 1.2-12V @ 1A. Use a LM317 regulator.
4) adjustable 0-12V @ 1A. Use a LM317 again, but now you need to work out how to get to zero volts. Hint: you need "negative" voltage.
5) fixed voltage 12V, variable current limit 0-1A. Use the LM317, a current shunt + amplifier, and your knowledge from lesson 4)
6) adjustable 0-12V, variable current limit 0-1A.
7) adjustable 0-12V, variable current limit 0-4A. LM317, pass transistor, current shunt + amplifier.
I do not recommend SMPS until you understand linear.
Question; you said you are a marketing executive. Do you plan to manufacture and sell your new power supply design on the market?
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Dear sir,
1) studied electronic circuits with neamen book. Haven't took Power electronics or smps course.
2) learn the analysis for a design and create a new own requirements for my design. No commercial moto.
Thank you
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My understanding:The diode and inductor, together with the previous transistor, form a DC-DC converter. The subsequent R8 and R9 are connected to the feedback pin of the chip. This is a classic DC-DC circuit — you can directly adjust the output voltage by modifying the resistance values of the feedback resistors.
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1) I could not understand the statement:
"If you eliminate the problematic ones, only one will remain - the regulation between Vref and the (-) of the amplifier."
Like this:
[attach=1]
You have the same thing on the website 320volt.com.
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1) Is the voltage error amplifier configured as a non-inverting or an inverting amplifier?
I'm not familiar with this IC, but find it interesting. From a glance of the picture in your first post, there are two op-amps in the IC. Their working mode will depend on how they are connected with the circuit outside the IC. In this circuit, the upper one is not configured with negative feedback, so I think it works as a voltage comparator (its output will swing to either the supply voltage, 32V, for high, or 0V, for low). The lower one has negative feedback loop so works as a real op-amp (conditional, due to the diodes not shown, may also work as voltage comparator under certain conditions).
[Due to the existence of the two unshown diodes, we may call these two op-amps working in a "source-only" mode.]
In this circuit, pin 1 will reflect half of the output voltage (\$V_o/2\$, which will be <16V for sure) – let's call it V1. Pin 16 is used for current sensing through the voltage drop over the shunt resistor R13, as input of the voltage comparator. Pin 15 has the reference voltage of 1V coming from a voltage divider. This means that any moment the current through the load goes above 10A, the output of the voltage comparator will swing to 32V. All other times its output gives 0V.
Let's start from a status when the load current is under 10A, i.e. the voltage comparator gives 0V. Its existence can be ignored given the back-to-back diodes between the two outputs of the two op-amps.
The (lower) op-amp will work to make the voltages on pins 1 and 2 match, meaning V2 will be \$V_o/2\$ (<=16V). There will never ot current flowing into or coming out of pin 2. Look at the loop at the bottom left corner; current flows from ref 5V through R3 and then R4 to ground. There will never be current flow through R5 either into pin 2 or through \$R_F\$ due to the internal diodes, ensuring the voltage at pin 2 to be not lower than 2.5V.
Any departure of \$V_o\$ from 5V will change this balance, and likely take the (lower) op-amp into action. You can figure the rest out ...
You might find this thread (https://www.eevblog.com/forum/beginners/understanding-uc3844-smps-controller-ic-block-diagram/msg6238683/#msg6238683) relevant and/or interesting ...
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Dear Sir,
1)You mean to say its an Inverting Amplifier with again -(51K/510). Is it Correct?
2) Why Inverting terminal has to be lower?
Your Statement" ensuring the voltage at pin 2 to be not lower than 2.5V",
Thanks you
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1)You mean to say its an Inverting Amplifier with again -(51K/510). Is it Correct?
2) Why Inverting terminal has to be lower?
Your Statement" ensuring the voltage at pin 2 to be not lower than 2.5V",
1) I don't quite care if it's inverting or non-inverting amplifier because I'm not working as a pro on a day-to-day basis and have all these standard circuits in my brain. I don't think you need to care either. All you should know is that when an op-amp is configured with negative feedback (i.e. output feedback goes back to the '-' input, or inverting input), the two golden rules (https://www.circuitbread.com/ee-faq/what-are-the-golden-rules-of-op-amps) apply (remember this is under the aforementioned condition). Then you analyze its behavior using these two golden rules. From here if you wish, you may then go further and understand why these two rules, based on the inherent characteristics of an ideal op-amp ( 1) infinite input impedance and zero output impedance; 2) infinitely big gain at the output of the difference between the two inputs, '+' - '-'. There is no need to remember the names "inverting" or "non-inverting" inputs, which are confusing and muddy the water a great deal).
[With this understanding, we will then know that, when without negative feedback loop, an op-amp will work as a voltage comparator, due to its inherent characteristics, mentioned above.]
2) What I mean is, in this circuit, due to the two unshown back-to-back diodes, there will never be current flowing through \$R_F\$ upwards. It's either no current or current flowing downwards. For the former case, the voltage on pin 2 will be the same as the lower end of R5 (since 0 current through it, too, so no voltage drop across it), which is 2.5V given by the voltage divider. In the latter case, the extra current (downwards through R5, coming from \$R_F\$) will give a voltage drop across it (this extra current will also make the voltage of the lower end of R5 greater than 2.5V, due to the greater voltage drop across R4 than across R3), making the voltage at pin 2 greater than 2.5V.
This is why I say, the voltage at pin 2 will never be < 2.5V.
For convenience, the two hidden diodes are shown in the attached block diagram. (Though interestingly, there are other differences in the internal configuration shown here comparing with your first post, which may change parts of my analysis above.)
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1)You mean to say its an Inverting Amplifier with again -(51K/510). Is it Correct?
2) Why Inverting terminal has to be lower?
Your Statement" ensuring the voltage at pin 2 to be not lower than 2.5V",
1) I don't quite care if it's inverting or non-inverting amplifier because I'm not working as a pro on a day-to-day basis and have all these standard circuits in my brain.
I don't think you need to care either.
It is important whether the amplifier inverts or not. Because this determines whether the feedback of the voltage regulator is negative (it will work) or positive (it will not work).
The gain will be equal to K=1+Rf/(Rf+R5+R3||R4)
R3||R4=R3*R4/(R3+R4)
I found that the yellow schematic linked by the ledtester comes from a Polish magazine ELEKTRONIKA PRAKTYCZNA 5/2009.
https://ep.com.pl/files/2439.pdf
https://serwis.avt.pl/manuals/AVT1522.pdf
The publisher also sold DIY kits, and I got this kit for free from a closed workshop. :)
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My understanding
"What I understand is that I should apply superposition, considering Vref one time and the op-amp output another time, which ensures that the inverting input becomes (2.5−0.000588)V, equal to 2.4999 V, ensuring that the voltage at the inverting input is not greater than 2.5 V."
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"What I understand is that I should apply superposition, considering Vref one time and the op-amp output another time, which ensures that the inverting input becomes (2.5−0.000588)V, equal to 2.4999 V, ensuring that the voltage at the inverting input is not greater than 2.5 V."
I used superposition when deriving the voltage at pin 2. But I'm not following what you said here.
The gain will be equal to K=1+Rf/(Rf+R5+R3||R4)
R3||R4=R3*R4/(R3+R4)
My instinct tells me your formula is probably correct (if using the Thevenin method, or Norton?). But I will verify myself with a closer look. I'm just not yet used to applying these methods in circuit analysis, but rather relying on the much slower, more cumbersome, and often unreliable intuitive approach.
That said, I'm not sure of the purpose of this voltage feedback (the lower op-amp as part of it) yet.
[Edit: It's actually fairly clear. The outputs, OR'ed after the two diodes, go to pin 3 for feedback, and also goes to the internal PWM Comparator, so regulating the duty ratio of the output signal...]
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The gain will be equal to K=1+Rf/(Rf+R5+R3||R4)
R3||R4=R3*R4/(R3+R4)
My instinct tells me your formula is probably correct (if using the Thevenin method, or Norton?). But I will verify myself with a closer look. I'm just not yet used to applying these methods in circuit analysis, but rather relying on the much slower, more cumbersome, and often unreliable intuitive approach.
That said, I'm not sure of the purpose of this voltage feedback (the lower op-amp as part of it) yet.
Yes, it can be done using the Thevenin method. Or the superposition method. The gain is equal to 17.(6)
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"I used superposition when deriving the voltage at pin 2. But I'm not following what you said here?"
What is that you were conveying? how do you applied super position?
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"I used superposition when deriving the voltage at pin 2. But I'm not following what you said here?"
What is that you were conveying? how do you applied super position?
I've attached the picture in your first post with annotations.
Where there is a red cross, that means no current in that part of the circuit, due to the "virtual open" golden rule of op-amp.
Then part of the circuit (in the green box) is under the effect of (potentially) two voltage sources. one 5V as shown, another, whatever output voltage present at the output of the two op-amps. We can consider there respective effect one by one (with the other ignored, i.e. as open) and superpose the two effects. (One shown with red arrows, another with blue arrow.)
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Looking closer at the (lower) op-amp and its voltage gain, I ended up with something in the form of:
$$V_o=a V_i + b$$
So the gain is dependent on the input voltage, not a neat constant. :palm:
Besides, is anyone able to tell what exactly that part of the circuit is for (the part in the green box, with the input into pin 1 included)?
More observation(s) of the circuit:
- Because pin 13 (output control) is connected to ground, which effectively disables the internal flip-flop, the two output transistors will be working in tandem, i.e. their timings are in sync.
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Dear sir,
1) studied electronic circuits with neamen book. Haven't took Power electronics or smps course.
2) learn the analysis for a design and create a new own requirements for my design. No commercial moto.
Thank you
Here's 1 prof that focuses a lot on SMPS's, they aren't exactly in a playlist, as far as I can tell
https://www.youtube.com/@sambenyaakov/videos (https://www.youtube.com/@sambenyaakov/videos)
IDK how much these 2 professor's cover SMPS, but they have lots of good video's, if you don't mind english. Not all these video's are under 'playlists' but once you start watching them, youtube lists the next videos
https://www.youtube.com/@b_razavi/featured (https://www.youtube.com/@b_razavi/featured)
https://www.youtube.com/playlist?list=PLc7Gz02Znph-c2-ssFpRrzYwbzplXfXUT (https://www.youtube.com/playlist?list=PLc7Gz02Znph-c2-ssFpRrzYwbzplXfXUT)
But there's ton's of other courses and short videos on all this stuff, if you watch youtube.
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Besides, is anyone able to tell what exactly that part of the circuit is for (the part in the green box, with the input into pin 1 included)?
All voltage regulators (linear and SMPS) compare a sample of the output voltage to a fixed voltage reference.
When the output voltage goes higher than the fixed voltage reference, the circuit cuts back the output.
When the output voltage falls below the fixed voltage reference, the circuit increases the output.
Regulation!
It is conceptually no different to a thermostat temperature regulator.
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Besides, is anyone able to tell what exactly that part of the circuit is for (the part in the green box, with the input into pin 1 included)?
All voltage regulators (linear and SMPS) compare a sample of the output voltage to a fixed voltage reference.
When the output voltage goes higher than the fixed voltage reference, the circuit cuts back the output.
When the output voltage falls below the fixed voltage reference, the circuit increases the output.
Regulation!
It is conceptually no different to a thermostat temperature regulator.
Thanks. I’m well aware of that. What I’m asking is, how is regulation done exactly and specifically in this case?
[Edit: Figured out, see Reply #19.]
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Thanks. I’m well aware of that. What I’m asking is, how is regulation done exactly and specifically in this case?
In this specific case, you actually need the datasheet to see what else is internally connected to the junction of the output of the two opamps.
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To facilitate analysis, attached is the same circuit based on the more detailed block diagram (with the Error Amp 1 sub-circuit copied in the box).
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Looking closer at the (lower) op-amp and its voltage gain, I ended up with something in the form of:
$$V_o=a V_i + b$$
So the gain is dependent on the input voltage, not a neat constant. :palm:
It is not possible for the gain to depend on the voltage; moreover, the formula you wrote does not include such a dependency.
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Looking closer at the (lower) op-amp and its voltage gain, I ended up with something in the form of:
$$V_o=a V_i + b$$
So the gain is dependent on the input voltage, not a neat constant. :palm:
It is not possible for the gain to depend on the voltage; moreover, the formula you wrote does not include such a dependency.
@max.wwwang @ommsiva
You skipped learning about simple regulators and now you have difficulty understanding it with a complex example. In the SMPS design materials, you won't find this knowledge because it's something everyone learns earlier.
Let's take a simple example of a linear regulator.
[attach=1]
I deliberately set a low amplifier gain and a high resistance R5 so that you can see how it works.
When the load current I1=1A appears, the voltage at the reg_out point drops. the voltage at point in_n also drops and the difference at the amplifier's input increases. The amplifier amplifies this difference by 100x, and at the amp_out point, a voltage rise appears that compensates for the drop caused by the load.
Real amplifiers have much greater gain, but the principle is the same.
Second example without an amplifier, the voltage drops almost to zero and the current does not reach 1A.
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Dear Sir,
I also Meant the Same. Thank you for your illustration.
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Take my simulation from LTSpice, try to run it and change the parameters.
What does the 51k resistor do in the first schematic? It reduces the gain of the error amplifier. In my example, I added R6 which serves the same function. What does it change? The gain is lower, the regulator works worse, and the voltage drop under load is greater. The likely reason for adding this resistor is to avoid oscillations, but this is not a sensible/recommended approach; it is advised to ensure that the gain for DC is maximized. And to achieve stability, the amplitude-phase characteristic is shaped only in the high-frequency range.
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Dear Sir,
Thank you.
My understanding is that by adjusting the feedback resistor to 10 kΩ, I can obtain a 5 V output in your simulation files.
Similarly, referring to my first question regarding output-voltage adjustment, my inference from this simulation is that the output voltage can be adjusted by changing R8. Is my understanding correct?
I have also attached the simulation results for your reference.
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..build a tester, might help in your understanding of the chip - though I failed to follow Richard's instructions, you may have more joy
https://www.youtube.com/watch?v=W66yahrJA5U (https://www.youtube.com/watch?v=W66yahrJA5U)
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My understanding is that by adjusting the feedback resistor to 10 kΩ, I can obtain a 5 V output in your simulation files.
At this moment, you don't have a functioning circuit, just a saturated transistor.
Notice that in my schematic, the power supply V2 has only 5V, which is too low for such a regulator to output 5V. Change V2 to a higher value, for example, 30V.
At the input in_p, there is 0.5V; to obtain 5V at the output, the divider R1,R2 must divide by 10, for example, 1kΩ and 9kΩ.
Since the amplifier has low gain, it won't give exactly 5V. If you go into the amplifier properties and change Avol to 100k (100000), which is closer to real amplifiers, it will be 5V.
Similarly, referring to my first question regarding output-voltage adjustment, my inference from this simulation is that the output voltage can be adjusted by changing R8. Is my understanding correct?
That's right, you can adjust the voltage by changing R8, but with this method, you won't get less than 2.5V because that's what you'll get if you set R8=0.
Derive the formula for voltage as a function of R8.
By replacing R3 and R4 (in my simulation) with a potentiometer, the voltage can be adjusted from zero.
The 5V regulator with a high-gain amplifier will work like this:
[attach=1]
The input voltage of the amplifier is below 1mV, so in simplified terms, it is said that the amplifier strives to achieve 0V at the input.
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Looking closer at the (lower) op-amp and its voltage gain, I ended up with something in the form of:
$$V_o=a V_i + b$$
So the gain is dependent on the input voltage, not a neat constant. :palm:
... moreover, the formula you wrote does not include such a dependency.
$$V_o / V_i = a + b / V_i $$
Thanks for taking the time to illustrate with an LTspice simulation, which I should development a habit of using...
I have a very specific question here:
There is a 0.7mA current source shown in the block diagram, replicated in this isolated subcircuit.[attachimg=1]
How would this current source affect the behaviour of this circuit? Suppose the voltage on the inverting input is also Vo/2, will this current be drawn through RF, or from the output of the op-amp, or a combination of both?
My guess is, since the ideal opamp has 0 output impedance, and has its power source, this 0.7mA current will entirely be sourced from the opamp. The problem with this is then, if so, with or without it, there will be no difference to the whole circuit (or the IC), which is impossible to be true, so would disprove my understanding. But why?
(Except for this last question, I think I've understood the working of this IC at the block diagram level. Thanks to @ommsiva for starting this topic.)
[Edit: more thoughts on the above question – I think my guess is probably the correct answer, assuming no voltage drop across the diodes. This means that the 0.7mA current source is solely due to the two diodes (otherwise would not be needed). But thoughts are welcome.]
[More edit: I figured out – assuming ideal diodes with 0V voltage drop, the 0.7mA current source only turns the otherwise source-only opamp back into its dual mode, i.e. source and sink, but with a 0.7mA ceiling for the sink mode. There will be sight difference from this due to non-ideal diode (and opamp), but the general principle and design intention should remain. But now I also realised a conceptual error in the block diagram: The output of the two opamps is internally connected to ground only though the 0.7mA current source. This must not be the case because if so, voltage on Pin 3, i.e. the input to the internal PWM comparator, would always be 0V. One option for the correction would be omitting the ground symbol on the left side of the current source.]
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From most outputs, we expect them to be able to both source and sink current. The direction of the current thru resistor Rf will depend on the output voltage. If there were no current source, it would not be possible to obtain voltages below 2.5V because the current thru the Rf resistor would have nowhere to flow.
[attach=1]
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Looking closer at the (lower) op-amp and its voltage gain, I ended up with something in the form of:
$$V_o=a V_i + b$$
So the gain is dependent on the input voltage, not a neat constant. :palm:
... moreover, the formula you wrote does not include such a dependency.
$$V_o / V_i = a + b / V_i $$
Thanks for taking the time to illustrate with an LTspice simulation, which I should development a habit of using...
I have a very specific question here:
There is a 0.7mA current source shown in the block diagram, replicated in this isolated subcircuit. (Attachment Link)
How would this current source affect the behaviour of this circuit? Suppose the voltage on the inverting input is also Vo/2, will this current be drawn through RF, or from the output of the op-amp, or a combination of both?
My guess is, since the ideal opamp has 0 output impedance, and has its power source, this 0.7mA current will entirely be sourced from the opamp. The problem with this is then, if so, with or without it, there will be no difference to the whole circuit (or the IC), which is impossible to be true, so would disprove my understanding. But why?
(Except for this last question, I think I've understood the working of this IC at the block diagram level. Thanks to @ommsiva for starting this topic.)
[Edit: more thoughts on the above question – I think my guess is probably the correct answer, assuming no voltage drop across the diodes. This means that the 0.7mA current source is solely due to the two diodes (otherwise would not be needed). But thoughts are welcome.]
[More edit: I figured out – assuming ideal diodes with 0V voltage drop, the 0.7mA current source only turns the otherwise source-only opamp back into its dual mode, i.e. source and sink, but with a 0.7mA ceiling for the sink mode. There will be sight difference from this due to non-ideal diode (and opamp), but the general principle and design intention should remain. But now I also realised a conceptual error in the block diagram: The output of the two opamps is internally connected to ground only though the 0.7mA current source. This must not be the case because if so, voltage on Pin 3, i.e. the input to the internal PWM comparator, would always be 0V. One option for the correction would be omitting the ground symbol on the left side of the current source.]
Dear All,
I admire all of you and the way you think. Many of the ideas and approaches discussed here are things that no one would have taught me otherwise. Alongside this, I am learning various avenues and different ways of analyzing and solving problems.
Thank you all for sharing your knowledge and insights.
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I built the aforementioned board, setting the voltages and currents was not a problem.
EDIT: It looked like the circuit was unstable, but it turned out that the wrong capacitor was included in the kit.
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Also, in case people haven't done their research, the schematic being discussed is within the TL494 application note;
https://www.ti.com/lit/an/slva001e/slva001e.pdf (https://www.ti.com/lit/an/slva001e/slva001e.pdf) (page 24)
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With a bit more work, I realised the error amp 1 sub circuit is equivalent to (I have been slow!):[attachimg=1]
So its voltage gain is (as discussed above, dependent on \$V_{i1}\$):
$$\frac{V_{o1}}{V_{i1}} = \frac{53}{3} - \frac{125}{3V_{i1}}$$So to answer your question 1, this amplifier is neither inverting nor non-inverting (or is both ... and ...). It is inverting for certain \$V_{i1}\$ range and non-inverting for another \$V_{i1}\$ range. The 'neutral' point is when the input voltage is about 2.358V, when the gain is 0.
That's why I said you don't really need to care whether it's inverting or non-inverting.
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So its voltage gain is (as discussed above, dependent on \$V_{i1}\$):
The gain is not dependent on Vi; the amplifier simply has two inputs and different gains for both inputs. You made the incorrect assumption that there is only one gain, and based on this mistake, you are misinterpreting the incorrectly transformed formula.
$$V_{o1} = (\frac{51000}{3060}+1)V_{i1} - \frac{51000}{3060}\frac{V_{ref}}{2}$$
$$V_{o1} = K_{i1}V_{i1} - K_{i2}\frac{V_{ref}}{2}$$
gains:
$$K_{i1}=\frac{51000}{3060}+1$$
$$K_{i2}=\frac{51000}{3060}$$
So to answer your question 1, this amplifier is neither inverting nor non-inverting (or is both ... and ...).
If we were to interpret the amplifier in isolation from its function, it would be so. But this is an error amplifier for which Vref is constant and the input voltage is the output voltage of power supply, and therefore at the input it is a non-inverting amplifier.
[/quote]
That's why I said you don't really need to care whether it's inverting or non-inverting.
If it doesn't matter, replace Vref with Vi1.
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So its voltage gain is (as discussed above, dependent on \$V_{i1}\$):
The gain is not dependent on Vi; the amplifier simply has two inputs and different gains for both inputs. You made the incorrect assumption that there is only one gain, and based on this mistake, you are misinterpreting the incorrectly transformed formula.
$$V_{o1} = (\frac{51000}{3060}+1)V_{i1} - \frac{51000}{3060}\frac{V_{ref}}{2}$$ $$V_{o1} = K_{i1}V_{i1} - K_{i2}\frac{V_{ref}}{2}$$
gains: $$K_{i1}=\frac{51000}{3060}+1$$ $$K_{i2}=\frac{51000}{3060}$$
I don't understand why it's a problem in us looking at the same circuit from different perspectives. I don't get where my "mistake" is. :)
As I said – and this is my personal view or preference (which by no means applies to anybody else) – I don't care what it is called as long as I have understood how it behaves. It's a bit like the question of whether someone should be called CEO, president, or boss – choose whatever you fancy. :popcorn:
This discussion is becoming more interesting than I though would be.
@ommsiva
By the way, since this circuit is from the application note, a close read of its section 5 would be very beneficial.
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In the circuit above, since the op-amp forces the inverting and non-inverting inputs to be equal (linear), a little analysis shows that Vo1 is zero when Vi1 is +2.35849V. This is the minimum Vi1 can be allowed so the output Vo1 is equal or above zero. Vo1 will increase with a gain of 17.6667 above that until the op-amp (saturates) and diode drop can no longer deliver the required Vo1 to keep the negative feedback loop linear, then the inverting and non-inverting inputs of the op amp deviate (no longer linear).
Anyway, hope this helps.
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In the circuit above, since the op-amp forces the inverting and non-inverting inputs to be equal (linear), a little analysis shows that Vo1 is zero when Vi1 is +2.35849V. This is the minimum Vi1 can be allowed so the output Vo1 is equal or above zero. Vo1 will increase with a gain of 17.6667 above that until the op-amp (saturates) and diode drop can no longer deliver the required Vo1 to keep the negative feedback loop linear, then the inverting and non-inverting inputs of the op amp deviate (no longer linear).
Anyway, hope this helps.
That helps. Thanks.
I'd be keen to hear your view on –
1) what I identified as an error in relation to the earthing symbol on the left hand side of the 0.7mA current source in the block diagram; and
2) what effect this current source has in the intended behavior of this circuit.
I feel pretty confident with my understanding, but shall, as always, remain open to the possibility that I might have missed something.
[Edit: very helpfully and very gratefully, I have been proven wrong in point 1). The earthing symbol should not be considered as an error, though still it may well be omitted. ]
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1) Believe the top of the current sink should be connected to the ground symbol, thus 0.7ma shunted to ground.
2) Its likely to keep the op-amp output always suppling current rather than sinking (which it can't due to the series diode), and always supplying current thru the diode so the op-amp output always sits at least a diode drop above ground when still in linear region.
Best
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1) Believe the top of the current sink should be connected to the ground symbol, thus 0.7ma shunted to ground.
Thanks. I presume you are referring to the circuit in Reply #41 (the earthing symbol that your are suggesting, was deliberately omitted). Not sure if you will change you view if looking at the (fuller) picture in Reply #28.
Why my suggestion of there being an error is because, with this earthing, the positive input of the PWM comparator will be permanently tied to ground, which would effectively disable both error amplifiers.
2) ... and always supplying current thru the diode so the op-amp output always sits at least a diode drop above ground when still in linear region.
This is a very good point regardless. It aligns with my understanding that, to answer my own question in some way (as I did already), the output of the opamp will be 'prioritized' in supplying this current, essentially without the current source affecting the behavior of the rest of the circuit.
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1) Believe the top of the current sink should be connected to the ground symbol, thus 0.7ma shunted to ground.
Thanks. I presume you are referring to the circuit in Reply #41 (the earthing symbol that your are suggesting, was deliberated omitted). Not sure if you will change you view if looking at the (fuller) picture in Reply #28.
Why my suggestion of there being an error is because, with this earthing, the positive input of the PWM comparator will be permanently tied to ground, which disables both error amplifiers.
2) ... and always supplying current thru the diode so the op-amp output always sits at least a diode drop above ground when still in linear region.
This is a very good point regardless. It aligns with my understanding that, to answer my own question in some way, the output of the opamp will be 'prioritized' in supplying this current, essentially without affecting the behavior of the rest of the circuit.
Yes #41.
See post #28, its shown correctly there. In this schematic you can see the current sense comparator (#2) and the error amplifier both have series diodes, this is a diode OR which allows either to set the PWM comparator level.
Best
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Yes #41.
See post #28, its shown correctly there. In this schematic you can see the current sense comparator (#2) and the error amplifier both have series diodes, this is a diode OR which allows either to set the PWM comparator level.
I suspect your are missing my point. I see all that you are saying, including the 'OR' of the two error amp outputs.
What I'm suggesting is that connecting the + input of the PWM comparator to ground through this current source means it will always have 0V voltage (at least so conceptually), making everything else connected to it useless (which I believe is impossible to be true).
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Yes #41.
See post #28, its shown correctly there. In this schematic you can see the current sense comparator (#2) and the error amplifier both have series diodes, this is a diode OR which allows either to set the PWM comparator level.
I suspect your are missing my point. I see all that you are saying, including the 'OR' of the two error amp outputs.
What I'm suggesting is that connecting the + input of the PWM comparator to ground through this current source means it will always have 0V voltage (at least so conceptually), making everything else connected to it useless (which I believe is impossible to be true).
The current source will simply draw the current from either of the diode OR connections. It will not force the voltage to ground, and simply assume whatever voltage is supplying the current. If its below the current limit then the feedback voltage side will supply the 0.7ma current and the voltage will be Vo1, when the current limit is reached then the current sense comparator overrides and the voltage (diode OR) and now this is the comparator high output minus a diode drop.
Best
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But since there isn't a voltage drop across a(ny) current source[Edit: unfortunately, this understanding is wrong], and its left hand side is at 0V (grounded, which is connect to the + input), wouldn't the voltage on the + input also be 0V (and always so)?
Have I made my point clear enough? Or am I still missing something? :)
Please do let me know if my way of thinking is either wrong, or just incompatible with the prevailing practice of using block diagram only to illustrate ideas roughly without that level of conceptual precision?
[Edit: indeed I was wrong. Thanks to @mawyatt! ]
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My conceptual interpretation is that of diode-OR logic;
https://en.wikipedia.org/wiki/Diode_logic#Active-high_OR_logic_gate
https://upload.wikimedia.org/wikipedia/commons/6/6e/Animated_wired_OR_diode_logic.gif
Obviously in the TL494 application we are dealing with continuously changing voltage level, rather than discrete binary voltage levels seen in logic.
Nevertheless, the concept is the same.
Consider what happens when both opamps are high and outputting/sourcing, say, 50mA each. That 100mA is going to overwhelm the 0.7mA, thus causing the voltage at that node to go high.
(50mA is an exaggeration, but hopefully you get the idea)
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I don't understand why it's a problem in us looking at the same circuit from different perspectives. I don't get where my "mistake" is. :)
As I said – and this is my personal view or preference (which by no means applies to anybody else) – I don't care what it is called as long as I have understood how it behaves. It's a bit like the question of whether someone should be called CEO, president, or boss – choose whatever you fancy. :popcorn:
Only when we all use a common language is understanding possible. Let's assume that one day you will be constructing a similar circuit and you ask about it on a forum.
So its voltage gain is (as discussed above, dependent on Vi1):
If you write that the gain depends on vi, no one will understand you. People will have a voltage-controlled amplifier in mind and will be wondering how someone attempted to use a VCA in a DCDC converter. People will be asking questions, and it will probably take a dozen posts and a few days to reach an agreement.
point is when the input voltage is about 2.358V, when the gain is 0.
If you write that the gain dropped to zero, similarly, no one will understand and they will be looking for an error in the circuit, an error that doesn't exist. If you used the word saturation, everyone would understand without discussion.
Your example of how we refer to a CEO is not adequate because you are using names that everyone knows. A better example would be if if you used the word tsfsd and expected people to understand that it refers to the CEO.
As I said – and this is my personal view or preference (which by no means applies to anybody else) – I don't care what it is called as long as I have understood how it behaves.
It's not a problem until you try to talk to someone about it.
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But since there isn't a voltage drop across a(ny) current source, and its left hand side is at 0V (grounded, which is connect to the + input), wouldn't the voltage on the + input also be 0V (and always so)?
Have I made my point clear enough? Or am I still missing something? :)
Please do let me know if my way of thinking is either wrong, or just incompatible with the prevailing practice of using block diagram only to illustrate ideas roughly without that level of conceptual precision.
You need to revisit how ideal current sources behave, then practical current sources. An ideal current source doesn't care about the voltage across it, the current will be "forced" thru anything regardless and produce whatever voltage results. A practical current source has limits which includes voltage levels and polarity.
Best
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You need to revisit how ideal current sources behave, then practical current sources. An ideal current source doesn't care about the voltage across it, the current will be "forced" thru anything regardless and produce whatever voltage results. A practical current source has limits which includes voltage levels and polarity.
Thanks for your advice. It's very helpful. This showed to me the challenge in truly grasping the concept of a current source.
A quick and simple thought experiment revealed my mistake. Supply a resistor R with an ideal current source. With this given current source, the voltage difference between its two ends depends entirely on the value of R and can be anything between 0 to infinity.
The say it a challenge for one reason at least. "Short' the two ends of an ideal current source does not result in a short circuit. There will only be an finite (as specified) current flowing through the apparent 'short' circuit.
I knew very well part of the concept that, no matter what, an ideal current source will make sure the specified amount of current flows through the line it is in, and certainly there will be limitations with one in practice. I only made a wrong assumption that the 'voltage drop' across it will always be zero.
Now go back to what I said was an error in the block diagram. The earthing symbol is NOT an error. But I still think it's ok, or even better, without it. For one reason, we can replace it with, say, the reference voltage 5V without any issue or any difference. Please correct me if, again, I'm wrong. (Believe me, saying this is not attempting to make myself look any good, or better. The circuit is all that I'm interested in.)
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Sure the ideal DC current source can be connected to anything, zero, 5, -5, 1000, -1000V and so on. Doesn't matter, linear or non-linear load, the current source will supply the DC current whatever the load conditions and load voltages are...it's ideal ;)
Practical current sources have a voltage range and polarity that needs attention. For example, you can't force a DC current into a +5V Voltage Source (Vref) unless the actual current source is biased above 5V somehow. You can sink DC current from Vref but you can't source current into Vref unless you use a higher than Vref bias in the current source.
Best
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Dear All,
1)My understanding is that the op-amp employed in the lower part of the schematic is operating in an inverting configuration. But why is it configured this way? The only reason I can think of is that it ensures the voltage at inverting terminal always remains lower than the non-inverting input. Please correct me if I am wrong.
2)The op-amp and diode form a super-diode configuration. When the non-inverting input is higher, the diode turns ON; otherwise, the pulse width has to be increased. However, I still cannot literally understand why there should be a 0.7 mA current source.
3)My understanding is that R1 = 1 kΩ should be made variable to adjust the current min-10A, and R8 should also be made variable to adjust the output voltage . Is this correct?
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1)My understanding is that the op-amp employed in the lower part of the schematic is operating in an inverting configuration. But why is it configured this way? The only reason I can think of is that it ensures the voltage at inverting terminal always remains lower than the non-inverting input. Please correct me if I am wrong.
I will analyze the diagram to see how the voltage changes at each point. It is important to check whether the feedback in the loop is positive or negative.
First, let's assume that the output voltage drops due to an increase in load (1.), which causes a drop at the amplifier's input (2.) and a drop at the amplifier's output (3.). The decrease at the amplifier's output causes an increase in the duty cycle (4.), which in turn causes an increase in the output voltage, counteracting (1.), meaning the feedback is negative. Since (2.) (3.) change in the same direction, the amplifier does not invert.
[attach=1]
2)The op-amp and diode form a super-diode configuration. When the non-inverting input is higher, the diode turns ON; otherwise, the pulse width has to be increased. However, I still cannot literally understand why there should be a 0.7 mA current source.
Assume that the output voltage at the cathode of the diode is 0.5V and analyze in which direction and where the current flowing thru Rf should go.
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2)The op-amp and diode form a super-diode configuration.
I'm not sure what a 'super-diode' is. But as the datasheet of the TL494 explains, the outputs of both error-amplifiers are OR-ed together. If the voltage of EITHER the 'voltage-regulator' OR the 'current-limiting' opamp becomes too high (or both at the same time), the output signal (after the diodes) becomes high and lowers the dutycycle of the PWM-circuit.
As to 1): you want a circuit that, when the input signal goes above a certain threshold, the output goes high. Thus you want a non-inverting amplifier. And that's how both error-amplifiers are configured in the schematic in your startpost: as non-inverting amplifiers (with negative feedback).
3) if you want adjustable voltage you could add a potmeter at R8/R9. For adjustable current, I'd make the value of R1 adjustable from 0-1kohm.
In one of my modified PC AT(X) PSU's I've implemented it differently though; see attached schematic. But that was for the modification of an existing AT(X) PSU; in your situation, I'd try adjusting the reference-level of the 'current'-error amplifier.
Keep in mind that by adjusting voltage and/or current, the overall loop-gain alters which could lead to instability (ringing, oscillation). I've managed to get all my homebuilt TL494 power supplies stable-ish, but I strongly doubt their control-loops are optimal. My excuse is that by education I'm an economist and mechanical engineer, not an electrical engineer.
If you want to learn more about control loops, Manfred Mornhinweg/XQ2FOD has written a relatively simple explanation about it: https://ludens.cl/Electron/loops/loops.html (https://ludens.cl/Electron/loops/loops.html)
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"Assume that the output voltage at the cathode of the diode is 0.5V and analyze in which direction and where the current flowing thru Rf should go."
Solution: Anode will be positive by 0.7V, means output of opamp should 1.2V. the opamp is acting as a current source. current flows to Rf through the diode.
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"Assume that the output voltage at the cathode of the diode is 0.5V and analyze in which direction and where the current flowing thru Rf should go."
Solution: Anode will be positive by 0.7V, means output of opamp should 1.2V. the opamp is acting as a current source. current flows to Rf through the diode.
The current flows from point V2 to Vo1, it cannot flow to the amplifier's output because the diode prevents it, so where will it flow?
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I continued testing converter #17 and the response to a sudden load change is fine. (tested at 15V 1A) However, the current regulator is oscillating. Set to 5A, it gives 10A peaks (oscillogram from the voltage on a 0.1Ω resistor).
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[Edit: see revised analysis in #74.]
I should correct myself again on what I said earlier that the internal 0.7mA current source will 'prioritize' the output of the opamp (through the diode). (My apologies – it's a learning journey to myself as well.)
Looking at the equivalent circuit of the ideal opamp, its output is modelled as a current source (rather than a voltage source). This means that there is no limitless current to be source from its output that can be prioritized (due to low impedance), and this opamp output and the 0.7mA outside the will need to reconcile with each other, which – when the reconciliation fails – has to be accommodated by the feedback loop, as far as it is capable of.
[attachimg=1][Picture courtesy of Microelectronic Circuits (https://www.tbooks.solutions/microelectronic-circuits-adel-s-sedra-kenneth-c-smith-7th-edition/)]
One question arises.
Suppose the voltage on pin 1 goes very low, for example 0V (which is possible if the upper end of R8 breaks open), the opamp will try hard to match this voltage at pin 2. But the best it can get will be 0V at pin 3, which only gives pin 2 voltage of 2.36V. (This gives a current of 46uA through RF.) Due to the difference between 0V on the non-inverting input and 2.36V on the inverting input, the opamp will desperately try to sink current, but only in vain due to the diode. This means it will be saturated with its output at 0V, with no current through the diode.
Now there is a shortage of 0.7-0.046=0.654mA in the required 0.7mA. I presume the result will have to be, due to compliance constraints, that the 0.7mA current source becomes a 46uA current source, the best it can do to 'comply' (because obviously, it's not ideal). Do you think so? (This is the question.)
This also demonstrates that, due to the diode, the opamp may operate as a voltage comparator (i.e. saturated) with certain input voltages at pin 1, when the golden rule of virtual short no longer applies.
(All pin identifications are those of the TL494 IC, which are different from those in the ideal opamp model above.)
Edit:
Based on this understanding, there are the following distinct operating modes corresponding to the input voltages (or voltage ranges) at pin 1:
- Pin 1 voltage <2.36V / opamp saturated (working in the voltage comparator mode) / voltage at pin 3 = 0V / 0.7mA current source is forced to comply. (In this mode the voltage at pin 2 will refuse to go under 2.36V)
- As soon as Pin 1 voltage becomes >=2.36V / opamp working as opamp with negative feedback (virtual short applies) / voltage at pin 3 = 0V / there will be a fight between the opamp and the 0.7mA current source, where the 'loser' (most likely the opamp) will be forced to comply.
- Pin 1 voltage =2.5V / as above / as above (this is the desired point)
- As soon as Pin 1 voltage goes >2.78V / as above / voltage at pin 3 reaches 5V / the required 0.7mA will most likely be satisfied by the opamp, which also supplies the current through RF. (This is when the PWM outputs are turned off – or earlier, depending on the exact voltage threshold)
(For all pin 1 voltages above 2.36, the opamp will always in the opamp mode, and the virtual short golden rule applies.)
1)My understanding is that the op-amp employed in the lower part of the schematic is operating in an inverting configuration. But why is it configured this way? The only reason I can think of is that it ensures the voltage at inverting terminal always remains lower than the non-inverting input. Please correct me if I am wrong.
As demonstrated above, the error amp 1 subcircuit (all included as a black box with pin 1 voltage as input and pin 3 voltage as output) works as either a nil gain converter (output = 0V) or non-inverting converter (positive output voltage, with positive input voltage), depending on the input voltage level. I still don't understand why its categorization is so important to you, but fine.
(Note that this is a revised interpretation from what I gave earlier, based on a refined understanding and an analysis at a more detailed and more accurate level.)
why is it configured this way? This is a hard one, depending on what exactly you mean, and also depending on the mode of thinking we are in. We are analyzing an existing circuit, with all components specified. So we are in a sort of 'reverse-engineering' mode of thinking. Working from all the given information, based on the established theories, we get the desired outcome (or verify if the outcome either by analysis, simulation, or prototyping, is what we expected). That's why. But if we are designing this circuit from scratch, that's an entirely different story.
2)... I still cannot literally understand why there should be a 0.7 mA current source.
To answer this in some way -- first remember why 0.7mA was chosen (as a design choice) must have been due to many factors, some of which are possibly not relevant to, or seen in, this example. Then, as demonstrated above, 0.7mA should be taken as its nominal capacity, and it can often be restrained to comply so will be supplying a less current (it's not an ideal current source).
3)My understanding is that R1 = 1 kΩ should be made variable to adjust the current min-10A, and R8 should also be made variable to adjust the output voltage . Is this correct?
Yes
My advice in short:
1) learn and understand the golden rules of opamp;
2) read the datasheet, again and again, over and over.
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Looking at the equivalent circuit of the ideal opamp, its output is modelled as a current source (rather than a voltage source).
That's not true. This is a voltage source. But in SMPS, you will also encounter amplifiers with a current source (operational transconductance amplifier).
This means that there is no limitless current to be source from its output
Real voltage sources always have limited current output. But it does not affect the basic circuit analysis. Even if it had unlimited current output, it wouldn't change the operation of the amplifier.
Now there is a shortage of 0.7-0.046=0.654mA in the required 0.7mA. I presume the result will have to be, due to compliance constraints, that the 0.7mA current source becomes a 46uA current source, the best it can do to 'comply' (because obviously, it's not ideal). Do you think so? (This is the question.)
True. A real current source is a transistor whose current decreases when the voltage across it drops below a certain level.
This also demonstrates that, due to the diode, the opamp may operate as a voltage comparator (i.e. saturated) with certain input voltages at pin 1, when the golden rule of virtual short no longer applies.
We talk about a comparator when the output can only take two states, like in the MC34063. A saturated operational amplifier is still an operational amplifier.
As soon as Pin 1 voltage becomes >=2.36V / opamp working as opamp with negative feedback (virtual short applies) / voltage at pin 3 = 0V / there will be a fight between the opamp and the 0.7mA current source, where the 'loser' (most likely the opamp) will be forced to comply.
When the voltage exceeds 2.36V, the diode conducts and the amplifier delivers 0.7mA. Since the amplifier has a low output resistance, the 0.7mA load does not affect the output voltage.
As soon as Pin 1 voltage goes >2.78V / as above / voltage at pin 3 reaches 5V / the required 0.7mA will most likely be satisfied by the opamp, which also supplies the current through RF. (This is when the PWM outputs are turned off – or earlier, depending on the exact voltage threshold)
The useful range of the PWM modulator is 0.5V-3.5V, which corresponds to an input voltage of 3.39-2.55V.
As demonstrated above, the error amp 1 subcircuit (all included as a black box with pin 1 voltage as input and pin 3 voltage as output) works as either a nil gain converter (output = 0V)...
Saturation occurs during transient states. It's like the needle of a gage moving beyond the scale; it's not a different mode of operation, we are simply outside the range of normal operation.
...or non-inverting converter (positive output voltage, with positive input voltage), depending on the input voltage level. I still don't understand why its categorization is so important to you, but fine.
If you use the TL494 as a converter controller, it matters. If you only used the amplifier, it wouldn't matter.
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Looking at the equivalent circuit of the ideal opamp, its output is modelled as a current source (rather than a voltage source).
That's not true. This is a voltage source. But in SMPS, you will also encounter amplifiers with a current source (operational transconductance amplifier).
This was not my invention. The picture comes from Microelectronic Circuits (source added in the post above). This is of course not saying that is the only way of modelling the ideal opamp.
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This was not my invention. The picture comes from Microelectronic Circuits (source added in the post above). This is of course not saying that is the only way of modelling the ideal opamp.
I think that was a clarification of your description of the picture.
The diamond symbol does NOT mean current source. The + and - symbols within the diamond indicate it to be a voltage source.
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The diamond symbol does NOT mean current source. The + and - symbols within the diamond indicate it to be a voltage source.
You are right here. Having checked out the book again, the output is indeed modelled as a voltage source. I was misled by the different symbol used for A(v2-v1) from those for v1 and v2 in the same picture. Thanks for your correction. :-+
And things are more lined up now. An ideal current source has 0 output impedance, which is consistent with 0 output impedance of ideal opamp. This means the output of ideal opamp cannot be modeled as an ideal current source (which has infinitely high output impedance).
I will update my analysis in #63.
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This is of course not saying that is the only way of modelling the ideal opamp.
You should learn the basics of electronics better. If you understood what a voltage source is and what its properties are, you would immediately catch your mistake.
To simulate the output of an amplifier that has a low output resistance, a voltage source with a low output resistance is ideally suited. Using a current source to simulate voltage source would be cumbersome. So you won't encounter the output of a classical operational amplifier modeled by a current source.
Some controllers like the SG3525 have a transconductance amplifier as the error amplifier. There, the output is current-based and the output resistance is high. If you can't distinguish between a current source and a voltage source, analyzing this circuit will turn your understanding of how an amplifier works upside down.
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Some controllers like the SG3525 have a transconductance amplifier as the error amplifier.
And on a tangent, the TL431 is often considered a transconductance amplifier.
What do you get when the control loop combines a TL431 with a TL494? :) (an extremely common configuration found in ATX power supplies in years gone by)
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1)My understanding is that the op-amp employed in the lower part of the schematic is operating in an inverting configuration. But why is it configured this way? The only reason I can think of is that it ensures the voltage at inverting terminal always remains lower than the non-inverting input. Please correct me if I am wrong.
To be clear, which schematic are you referring to?
2)The op-amp and diode form a super-diode configuration.
Not really "super-diodes" (i.e. precision rectifier circuits). The diodes are there in order to allow either opamp (which ever one has the higher output) to take control of the voltage at pin 3. Without the diodes, the opamp outputs would be short circuited together, which would be problematic for multiple reasons.
When the non-inverting input is higher, the diode turns ON; otherwise, the pulse width has to be increased.
Correct, non-inverting input increasing causes the opamp output to increase, which may cause pin 3 voltage to increase, causing the PWM duty cycle to decrease.
However, I still cannot literally understand why there should be a 0.7 mA current source.
Because of the diodes on each opamp's output, it's only possible for the opamps to source current into pin 3. The current source is there to help pull pin 3 low when neither diode is forward biased. Without that current source, the error amplifier circuits would not behave as expected.
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Dear Sir,
I am refering to attached circuit.
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I see what you mean with super diode now. It’s interesting (https://www.reddit.com/r/chipdesign/comments/1byb0im/how_does_the_superdiode_circuit_work_can_someone/). Also precision rectifier (https://en.wikipedia.org/wiki/Precision_rectifier).
No, as suggested, the opamps and the diodes here are not intended to work as super diodes.
[I like the term 'super diode', partly because I prefer the term "ideal diode" to be reserved for a conceptual diode that is similar to super diode but with a non-zero voltage drop, i.e. a one-way switch with a voltage drop. This makes sense even with respect that a super diode is in a way superior than an ideal diode (though some might find it uncomfortable to have something superior than ideal). :-DD]
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Dear Sir,
I am refering to attached circuit.
In this case that opamp circuit is acting as a difference amplifier. Its output will be roughly (Vout-Vref)*10. Though this will be only be the case if the other opamp is not in control of pin 3.
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(https://www.eevblog.com/forum/index.php?action=dlattach;topic=489854.0;attach=2847124;image)
[Picture courtesy of Microelectronic Circuits (https://www.tbooks.solutions/microelectronic-circuits-adel-s-sedra-kenneth-c-smith-7th-edition/)]
This is a revision of my analysis in #63 of the voltage regulator feedback subcircuit. It is based on the following assumptions or premises:
1) ideal opamp with a voltage source as its output;
2) 'ideal diode' (my term – meaning an ideal one-way switch but with a non-zero voltage drop when on, which is assumed as 0.7V here [Edit: actually this does not matter; furthermore, this assumption is not necessary.]);
3) single voltage supply for the opamp, meaning its output will not go under 0V (as constrains for the 0.7mA current source when it has to 'comply');
4) the current feedback opamp is not firing up.
All critiques are welcome.
It's based on this equivalent circuit:
[attachimg=1]
An ideal opamp will be capable of sourcing or sinking any current required by a current source connected to its output. Due to the diode however, only sourcing is possible. And due to the 0.7V voltage drop, sourcing is possible only if/when the voltage source at the opamp's output is 0.7V or above.
This means, still, my previous statement "the 0.7mA current source will prioritize the opamp outputs" is not true. As long as the opamp output voltage remains <0.7V, this current will come solely from the path of RF.
Consider some typical scenarios:
1. When there is a 0.7mA current flowing from +2.5V through RF, just meeting the needs of the current source.
Theoretically this will give a voltage of 0.358V at pin 2 and -35.342V at pin 3 (or output voltage). Due to constraints (output voltage is impossible to go under 0V), the result will have to be the following scenario –
2. A current of 46uA is flowing through the same path, giving 2.358V at pin 2 and output voltage of 0V.
The current source is forced to comply and becomes a 46uA current source. This happens whenever pin 1 voltage is under 2.358V (when the diode will remain off).
Still, there will be the following modes of operating based on pin 1 voltage (or input voltage):
- Input voltage <=2.358V / the diode is off / the 0.7mA current source is forced to comply and downgrades to 46uA current source / the opamp is saturated (effectively working in a voltage comparator mode) / output voltage = 0V .
- As soon as input voltage becomes >2.358V / the diode turns on / the demand of the 'starving' 0.7mA current source is immediately met (with the shortage met by the opamp) / the opamp working as opamp with negative feedback (the virtual short rule applies) / output voltage starts to rise from 0V.
- Before input voltage reaching 2.5V / the diode remains on / the 0.7mA current source is pumping 0.7mA through (supplied by both the opamp and through RF) / the opamp working as opamp with negative feedback (the virtual short rule applies) / output voltage keeps rising (now between 0V and 2.5V).
- When input voltage reaches 2.5V / the diode remains on / the 0.7mA current source is pumping 0.7mA through (but now supplied soley by the opamp, no current through RF) / the opamp working as opamp with negative feedback (the virtual short rule applies) / output voltage reaches 2.5V. (This is the desired point.)
- As soon as input voltage goes >=2.642V / the diode remains on / the 0.7mA current source is pumping 0.7mA through (but the opamp is now supplying the current for both of the 0.7mA current source and through RF) / the opamp working as opamp with negative feedback (the virtual short rule applies) / output voltage reaches 5V. (This is when the PWM outputs are turned off – or earlier, depending on the exact voltage threshold.)
Here is what I get as the relationship between V1 (input) and V3 (output):
[attachimg=2]
This shows that the voltage regulator subcircuit is either a nil gain converter or a non-inverting converter, depending on the input voltage.
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Here is what I get between V1 (input) and V3 (output):
(Attachment Link)
Right, and this is exactly what you would expect from a normal opamp without any output diode or current sink.
The only time when the circuit won't act like a basic opamp is:
1. The 0.7mA current sink becomes a limitation. Most common example would be if there is significant capacitance on pin 3. For example, if there is 10nF on pin 3, then the voltage at pin 3 would not be able to slew downwards faster than 70,000V/s (this could be a good thing or bad thing, depending on what you want).
2. The other opamp output is higher, in which case it will take control of pin 3.
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Here is what I get between V1 (input) and V3 (output):
(Attachment Link)
Right, and this is exactly what you would expect from a normal opamp without any output diode or current sink.
The only time when the circuit won't act like a basic opamp is:
1. The 0.7mA current sink becomes a limitation. Most common example would be if there is significant capacitance on pin 3. For example, if there is 10nF on pin 3, then the voltage at pin 3 would not be able to slew downwards faster than 70,000V/s (this could be a good thing or bad thing, depending on what you want).
2. The other opamp output is higher, in which case it will take control of pin 3.
Thanks. But your response is not clear to me. Is my result correct for the circuit (including the current sink and the output diode)?
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Thanks. But your response is not clear to me. Is my result correct for the circuit (including the current sink and the output diode)?
Your analysis is correct, my point is that such a detailed analysis isn't really necessary.
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Thanks. But your response is not clear to me. Is my result correct for the circuit (including the current sink and the output diode)?
Your analysis is correct, my point is that such a detailed analysis isn't really necessary.
I know. In experienced/educated eyes it's as plain as .... But to me, it takes effort; and getting here only after so many blunders. :palm: