How to reduce possible environmental noise when testing

[LoveLaika]

I have a self-contained current-to-voltage amplifier circuit that I'm looking to test. I included a schematic of the amplifier below, with the elements in the dotted box being the enclosed amplifier circuit. It is sealed in a grounded box, so the inputs and outputs to it are power supply voltages, a bias voltage, the input current signal, and the output. Under regular operating conditions, the input current is in the range of nano-Amps, and I don't have any equipment that can act as a current source. The way I plan to test it is by introducing a load resistance to ground, R_LOAD. Using circuit analysis and a given bias voltage, I can calculate what the output voltage will be by adjusting R_LOAD. The output voltage will be going into an oscilloscope, represented by R5.

The problem I'm concerned about is the possibility of noise at the input. The environment that I'm testing this in is quite noisy; because I'm using through-hole resistors to accomplish the testing (by using a breadboard to hold them in place), I'm concerned that they might pick up excess noise in the environment. Under normal operation, the output of the op-amp was picking up some low level 20 Hz noise which is causing problems for the rest of the circuit. The goal for this testing is to see how the op-amp circuit behaves given a clean input signal. If the output signal is clean, then we know there's something wrong with our input current signal that is introducing noise. Having the resistors on a breadboard sounds good in prototyping, but I read that breadboards can pick up unwanted noise in a circuit. Is there any way to avoid this occurrence, or perhaps there is a better way to approach this testing method?

EDIT: After much consideration, I found that the best way is to use a perf-board to hold my resistors. It's a bit inconvenient, but it's non-conductive, so there shouldn't be any stray parasitic components or noise. I guess that makes my question moot. However....looking at the diagram once again, I can't help but wonder: is it possible that a voltage potential induce noise somehow? So, the PCB that my op-amp circuit is on has a copper pour tied to the BIAS voltage, not ground. This is because that was how the original current-to-voltage op-amp was designed. The op-amp and its components were "referenced" to the bias voltage, as if it were ground. The case holding op-amp is actually tied to ground, and it is electrically isolated from the PCB (there's non-conductive material holding the PCB in place, so it is not touching the case). Seeing as how there's a difference in potential from the case and the PCB ground plane, is that to be concerned about?