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HP 16500 Logic Analyzer "doesn't like" clock signal (thinks it's always high)

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Phaseseeker:
Pretty much as the title states; HP16500 + 16510 State/Timing card, in state mode. The analyzer complained about the clock being slow or missing, so I connected it to one of the input channels (same pod) and it sees it as always high. I checked with a scope and the clock is there, there's a bit of ringing but it might be caused by the way I was probing it, either way the device that uses that clock runs without issues.
The clock signal in question is a 4MHz clock being generated from an ATTiny85 with TMR0 in CTC mode (internal oscillator set at 16MHz and divided by the timer to 4MHz); I did this because I didn't have an oscillator module of the right frequency and the device under test doesn't have the ability to output a clock when run from its internal oscillator.

jmelson:
I use Tek analyzers.  But, can it view the clock channel as an ordinary data channel in timing mode?  That would allow the analyzer to self-clock.  Then, you could tell if the clock channel was bad, or not connected.  Does this analyzer have variable logic levels?  Check what logic voltages it is set for.
Jon

Phaseseeker:
I did some more testing, turns out the problem was in what HP calls "tip isolation network", basically a small RC circuit which is put in series with each channel to terminate the cable. I made my own PCBs with said RC networks and turns out I managed to swap two of the resistors on some of the lines. Obviously the last place I checked, since I had already used the PCBs without issues (on systems with slower clocks)...
Thanks anyway

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