Help with fault pin on DRV8701 gate driver.

[no1no2no3no4]

Hi, quick question about the fault pin on the DRV8701 gate driver. I'm looking at the data sheet(https://www.ti.com/lit/ds/symlink/drv8701.pdf) and it states for the nFAULT pin "Pulled logic low with fault condition; open-drain output requires an external pullup". I'm not exactly sure how to interpret this. What output voltages am I expecting on this pin? Would it be high when there is no fault and low when there is a fault? And I'm also assuming the voltage would be the same as the logic input, for example if I'm using 3.3V, the output on this pin would also be 3.3V.

[pcprogrammer]

In this case it being open drain means that it is based on a n-channel FET where the drain is on the pin, the source is on ground and the gate is controlled from the internal logic. It needs an external pullup to the desired voltage level for your logic. Probably the 3.3V you mentioned.

The datasheet might state a maximum voltage that can be used on the pullup.

If it states that it is pulled low in case of a fault, then there is a fault condition when you see it as a low and not when you see it as a high.

Edit: the datasheet states that the pullup on nFault needs to be >= 10K Ohm. See table "External Passive Components"
It also states that the absolute max voltage on this pin is 5.75V and the current should not exceed 10mA.

[Zero999]

The pin has a switch which connects it to the 0V pin, during a fault condition. It needs a 10k or higher resistor connected to VDD to enable it to output a logic high.

A detailed schematic showing how this is done can be found on page 13 of the data sheet.

This arrangement is very common, especially for comparator ICs, e.g. LM311, LM393, LM339.

[no1no2no3no4]

That makes perfect sense. Thanks!