ICM7555 timer IC: Duty cycle limitations at higher frequencys?

[Faringdon]

Hi,
ICM7555 has a max frequency of 500kHz. (T=2us) However, pg 8 Fig 9 says there is a ~250ns propagation delay when vdd=5v.
That must mean that the duty cyle when at 500kHz must be limited to 0.75 maximum?

ICM7555
https://www.nxp.com/docs/en/data-sheet/ICM7555.pdf

Do you know what the max duty cycle can be of the output at 120kHz?

[Zero999]

At 500kHz the on/off times are 1µs.

The period of 120kHz is 8¹/₃µs.

I would go with 7.333/8.333 = 88%

[Faringdon]

Thanks, so you mean our pulse circuit as attached is not going to be possible? (LTspice and jpeg attached)
It provides a train of 400ns pulses at 240kHz. The pulses shouldnt really be wider than 400ns,  deffo no wider than 500ns.

So would need a low time of 400ns out of the ICM7555...apparently this is impossible?.....its for syncing  two UCC28070A's in quadrature. (4 boosters total)

I am amazed the ICM7555 datasheet doesnt give the maximum achievable duty cycle over swept frequency.
...or just tell what the  minimum "Low time" achievable is.....it is after all, a timer chip.

[Zero999]

Build it. This is something LTSpice will not answer.

[Faringdon]

Youre right i should breadboard it...but i think it'll be quicker at this point to re-lay the board as the attached.
I am moving into a lab unit soon, to put this all together, and i have to order all the kit etc, so i wont have time to build a breadboard of it now....getting a new PCB from China will be cheap.

Any improvement on the attached well appreciated......Many thanks to yourself Zero999, as now i am pretty sure that ICM7555 wont be able to reliably do much less than 1us output pulse width......i need <500ns for the UCC28070A sync pulses (my fsw is 60khz for each booster)

i may just use SOT23-5 gate drive ICs instead of the buffers...the buffers only come in SOIC16.

[jpanhalt]

I suspect there are dedicated PWM controllers that will do what you want.  If not, it would seem easy to do with a microcontroller. Assume a PIC operating at 16 MHz (common 8-bit ones easily go to 32 MHz).  The instruction time is 250 ns (16 MHz/4 = 4 MHz system clock = 250 ns per clock cycle (Tcy)).  Using 1-cycle instructions should give a 250 ns pulse then a delay.  Here is some off the cuff untested code.  Assume the output bit you want to toggle is PORTA,0 (or LATA,0 for those with output latches.

Code: [Select]

Start
bcf PORTA,0
movlw 0x01
Pulse
xorwf PORTA,f ;PORTA = uuuuuuu1 where u = unchanged
xorwf PORTA,f ;PORTA = uuuuuuu0 (elapsed time = 1 Tcy)
Delay
; add whatever delay you need for low
goto      Start+1
end
Of course, how fast it really toggles will depend on how much capacitance it is feeding. One might use bcf/bsf pairs, but bit instructions can cause problems known a RMW (read-modify-write) errors.  Using output latches cures that.  I would recommend an enhanced mid-range or later chip with output latches.  The 10F320/322 are available as a 6-pin device in an SOT-23 package or 8-pin DFN package.

[Faringdon]

Thanks jpanhalt...i'd say that looks the best way...nxt time i will do it in code...but for now, its way past build time and i have to get this built and move into the lab......i also dont have pickit 3 any more and i hear microchip have gotten rid of it.

The attached is the way for now...
The attached is the finished version of 400ns pulse trains...any (in analog) improvements greatly appreciated...(LTspice and jpeg)

[Zero999]

What's with four LTC1693-3s, rather than two?

How accurate does it need to be? You do know that an analogue design will have an tolerance of 5% at best.

[Faringdon]

What's with four LTC1693-3s, rather than two?

..Thanks, tried it with two, pulse not as "tidy".

Thanks, yes, 5% is  fine.....UCC28070A  sync pulse must be longer than 200ns.....preferably no longer than 600ns if fsw is 60khz say.
The sync pulse length will detract from the UCC28070A duty cycle...so in other words, the effect of a too_long sync pulse, is too_short max duty cycle of the UCC28070A..

Also, ive noted, the gate driver input is not schmitt trigger protected, so there is a danger of double pulsing...as such, the attached is now the finished version.....any improvements greatly appreciated?

[Zero999]

The LTC1693 does have Schmitt trigger inputs. RTFDS.
https://www.analog.com/media/en/technical-documentation/data-sheets/1693fa.pdf

[Faringdon]

Thanks....thats interesting......actually, sorry to have omitted to say, but in the actual cct i am using UCC27533 (because its elsewhere in the BOM).....i assumed LTC1693 would be too expensive, but will check now....Actually no...i think the 74HC123 solution above is the  best way...i think ill stick with it.....should you disagree, comments greatly appreciated.

[Zero999]

Why not replace the 555 with a CMOS oscillator using some of the free NOR gates in the 74HC02 package?

By the way, LTSpice is smart enough to know if you leave gate inputs disconnected, you're not using them.

[Faringdon]

Thanks, my NOR gate oscillator skills seem to have vanished on me...

[Zero999]

You do know the logic gates built into LTSpice are just idealised models?

I made my own using MOSFETs based on the 4007.

The classic two gate circuit didn't work, but the three gate oscillator was a success. This shouldn't be surprising since the two gate circuit can be a little flaky, especially at higher frequencies.

D1 and D2 represent the protection diodes, which are important for the first gate as the voltage on one side of C1 exceeds the supply rails. I've not bothered with them on the other gates because they never conduct.

The output waveform isn't nice. It's better taken from M1.