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important frequencies in high speed digital signals

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tyblu:
I started derailing a topic, so I've recreated it here to avoid a full-fledged hijack.

--- Quote from: tyblu on November 27, 2010, 05:30:23 pm ---USB 3.0 can burst up to 5 Gbps using 2 full duplex lines, according to the great Wiki. The two 2.5GHz signals will have to have to be treated as RF with important frequency components up to 10x their switch frequency, or 25 GHz. Maybe some of this cost covers a VNA? The device inputs will have to have a broadband match up to 25 GHz, or at least have a match characteristic simple enough for which to compensate. Seems wonderfully difficult to me!
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--- Quote from: tyblu on November 27, 2010, 06:17:11 pm ---...
I know that one should consider digital lines at 10x their switching frequency when laying out power paths and signal traces (keep traces less than 1/10 of a wavelength), but what about when you're trying to take the TL effects into account? Do you really need all components within 10x (9x or 11x, really, as even components are 0) its switch frequency, or can you just match up to 5x (2nd fundamental)? ie: Is the 10x rule of thumb just for avoiding TL effects in PCB layout, or is it even more generalized, applying to RF design? Yeah, I know, go to RFCafe already.
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--- Quote from: allanw on November 27, 2010, 07:03:34 pm ---
--- Quote from: tyblu on November 27, 2010, 06:17:11 pm ---[As an aside, I know that one should consider digital lines at 10x their switching frequency when laying out power paths and signal traces (keep traces less than 1/10 of a wavelength), but what about when you're trying to take the TL effects into account? Do you really need all components within 10x (9x or 11x, really, as even components are 0) its switch frequency, or can you just match up to 5x (2nd fundamental)? ie: Is the 10x rule of thumb just for avoiding TL effects in PCB layout, or is it even more generalized, applying to RF design? Yeah, I know, go to RFCafe already...]

--- End quote ---

I've been reading Howard Johnson's books and they've been very informative. I believe this is my understanding of his material:

For digital signals, what you need to worry about are the rise/fall times of the signals, as these are the actual high frequency content of your digital signals. He says: "Most energy in digital pulses concentrates below the knee frequency: 0.5/Tr", where Tr is the rise time. "The behavior of a circuit at the knee frequency determines its processing of a step edge. The behavior of a circuit at frequencies above Fknee hardly affects digital performance"

But then the question arises as to what the rise time of USB3 signals are. I don't know.
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tyblu:
I'm not sure what the author means by knee frequency -- maybe on a PSD graph for a single pulse? That is useful when you want to recreate the signal nearly exactly, for example in a DSO where BW must be >0.35/tr (RC-type rise/fall), but not so much when all you want to do is extract the logic levels. For example, a UART signal may only be transmitting at 9600 baud but have a rise time at the driver end of 2.2ns. This signal does not need to be over-sampled at 0.5/2.2ns=230MHz or 0.35/2.2ns=160MHz in order to read it, only about 20kHz (Shannon's theorem).

Of course, there is no reason to worry about matching loads to lines with a 'kHz signal, but say you had a 2Gbps signal (USB3.0) on a 2m-long full duplex twisted pair line going into a level shifting IC with high impedance inputs. This signal will have frequency components at (2n+1)*2GHz, where n is any integer (harmonic), and will fall off as 1.3/(2n+1). If the input is made to match only 2GHz signals it is essentially low-pass'ing out the rest, smooshing the square wave into a sinesoid'ish monster -- is this so bad? It'd say yes, as if it is being sampled at ~4GHz, it has a high chance of never reading a valid 1 or 0. If the input is matched to the next fundamental, 6GHz, though, then a ~4GHz sample rate will likely read the value in the 'ripple' area of the signals. Are these 'rippled' areas completely within the realm of valid logic?

Which brings up another question: what is defined as valid logic? I've been taught that valid digital output must be <10% or >90%, and valid digital input must be <40% or >60%. The fundamental (n=0; monster sinusoid) would probably pass as a <40% or >60% signal, but not a <10%, >90% one. Does this mean a flip-flop that accepts the lax input range would correct for poor input impedance matching?

allanw:
What he means by knee frequency is the frequency at which signals must be passed in order to not increase the rise time. At very low baud rates, this isn't a good metric, but it makes sense for faster digital signals.

Also at high frequencies, transmitters use pre-emphasis and receivers use equalization to boost high frequency signals (transitions) while lowering the signal strength of constant voltage levels. This is to balance out the skin effect losses which depend on frequency. I believe this preserves the square wave of the signal. Something like this image:

http://i.cmpnet.com/planetanalog/2009/02/C0351-Figure3.15.gif

tyblu:
That's right; I've seen it emphasis used in radio communications. I haven't had the chance to use eye diagrams before, but they seem to be pure genius. Pre-emphasis may be standardized, but what about the inputs? The 'equalizer' is tuneable, I imagine? And any idea what the minimum signal level needs to be at off-fundamental frequencies (ie: 6GHz for a 2GHz clock; eg. min -20dB tunable), or a part number with a decent datasheet?

Time:
Take your rise time as a half period and model around that for a frequency.  Its probably more accurate than your fundamental.

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