MOSfet theory simplified:
You can treat a MOS fet as a voltage controlled resistor.
If Ugs (Gate - Source Voltage) is below some threshold (usually 3 to 5V) then the resistance between source and drain is high (> Meg Ohm)
If Ugs is above that threshold, then the resistance between source and drain is low.
This works for both P- an N- channel MOS fets, but the polarities are reversed (not the pins).
What happens in your first circuit:
If "FROM_FPGA" is high, then the source drain channel "opens" (to a low resitance) however, because of the current though R11, the voltage on the source also rises, and this causes Ugs to get smaller. The voltage on the source will settle about "Ugs" lower then the gate voltage, because that is when the MOSfet starts to squeeze the current by increasing it's drain to source resistance.
So your particular 2N7002 has an Ugs of 3.3 - 1.65 = (also) 1.65V.
But it's not a voltage divider. Ugs will be (almost) stable.
If you for example put 12V at the drain and 8.65V on the gate, then the source will settle at 7V.
If I remember well, Wikipedia has a quite good explanation of MOS-fets (and other electronic components), but there is plenty of literature.
Also:
You can DIY a level shifter, but these are so common that you can get breakout boards for level converters quite cheap. Order some the next time you order some electronic stuff.
Another note about KiCad:
I see a little green (open) square on the gate of your MOSfet. This means an open wire end at that location. If wires end neatly at the connection points of schematic symbols, then you also do not see junction dots there (as with your resistors and the GND symbol)
In your circuit it's not a real problem (although ERC may flag it). But such things sometimes cause problems, and when you use KiCad more, you'll probably become just as allergic to seing those squares as I have become. Those open squares always are an indication that the schematic needs a bit of cleanup.