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| Integrated Regulated power supply |
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| IanMacdonald:
The problem with this arrangement is that if P2 has a bad spot on its track the output will go to max and likely damage the circuit under test. Better to have the pot in the +ve input (pin 5) and a fixed feedback ratio. Only thing is, to get low voltages you then need an aux supply for the 723. |
| xavier60:
--- Quote from: techguru on June 10, 2018, 05:18:35 am ---Here is the clear calculation sir.. Please help me... --- End quote --- Keep in mind that you should be calculating divider voltages With Respect To ground, pin 7 of the LM723. |
| Simon:
--- Quote from: DC1MC on June 10, 2018, 05:13:22 am ---I want to, but I can't, calculating 135mA and voltages on that schematic showed that you don't have the basics and you need much more learning before starting with this kind of schematics, sorry. --- End quote --- Then why reply to the thread? if you think something is amiss then report it. I encourage you to spend the next 3 days thinking about the extreme value in keeping your big mouth SHUT if you have no intention of helping and are considering stirring things up. Well what you do with the next 3 days is up to you but you certainly won't be spending them on here doing very much..... |
| techguru:
Thanks a lot cellularmitosis... |
| techguru:
hi to all.. 1)why we have Q1(pnp) and Q2(npn)? According to me it is Q2 which is going to act as external series pass element. 2)But why do we have Q1 there and Internal series pass element collecter connected to base of PNP transistor what is the logic present there? According to me collector of the series pass transistor should be connected to maximum positive voltage(not exceding 40V). what will happen now? 3)why emitter of internal series pass transistor connected to 220 ohm ant that is connected 68 ohm. A voltage divider is formed and it is connected to output? Emitter of internal pass transistor should be connected to external series pass transistor but why it is being connected to voltage divider and to output? still i am not clear in this schematic? Kindly help me to understand? |
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