Author Topic: Interfacing with TI ads1278 ADC with Cyclone IV FPGA  (Read 2611 times)

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Offline rsridharTopic starter

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Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« on: July 07, 2018, 06:01:15 pm »
Hi All!

Im trying to get my Altera FPGA to talk with a TI ads1278 ADC:
http://www.ti.com/lit/ds/symlink/ads1274.pdf

This is my first time trying this; and Ive only ever used my FPGA with a much simpler ADC.  But Id like to get this fancy Delta/Sigma one up and running.

I put together what I thought would get the adc up and running, but all I got was my ADC getting really hot; and outputting a constant "0". So something is wrong.  I have some very basic questions as this is my first ever time using this adc:

1. The ADC has lots of repeat pins; for example there are 5 analog gnds, 4 analog power supplys, 4 Digital Gnds, 4 Digital power supplys.  Do all of these need to be connected?  Or is connecting one sufficient?

2.  What is the difference between Analog gnd and Digital Gnd?  Is there any advantage in setting them differently?

3. There is an Analog power (4.7-5.25V); a Digital power supply (1.65-3.6V).  But what about the following pins, do they need to be connected:
-VCOM AVDD/2 Unbuffered voltage output
-VREFN Analog input Negative reference input.
-VREFP Analog input Positive reference input.
-DVDD Digital power supply Digital core power supply

4.  Overall, if you look at the timing plot on page 8 for the SPI interface; I am setting Drdy low every 512 clock cycles (using High Resolution mode, so Fsample/Fs=512).  Is this correct?

5.  I am using a housing which takes the ADC package and converts it to dip switches.  Im using jumper cables to connect the dip switches on the ADC adapter to DIP pins, which Im using jumper cables to connect to the FPGA's pins.  The adapter looks like this:
https://www.ebay.com/i/172825294343?chn=ps
Any possible issues with this adapter?  My signals are running at a max of 25MHz through the cables conecting them; the cacbles are all under 6".


6.  Is the sigma delta ADC supposed to get this hot?  it smells like it may start melting; but I may have had it connected incorrectly.

Thanks, Id apreciate any guidance on this!
 

Offline KaneTW

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #1 on: July 07, 2018, 06:13:53 pm »
1) Unless specified otherwise, they all need to be connected (to the right voltages respectively)
2) If you have a separate ground plane for analog and digital, tie them together at the ADC. It's a complicated topic, and usually fine to use the same ground unless you need the performance.
3) IOVDD needs to be within 1.65-3.6V, DVDD depends on the frequency you run the ADC at, check the datasheet.
  VCOM is an output pin for AVDD/2, VREFN/P is for connecting a reference voltage. Specifically, this ADC doesn't seem to have an internal reference, so connect it to an appropriate voltage reference (check data sheet).
4) You're not supposed to set DRDY low. DRDY is an output pin that indicates that a reading is available.
5) You'll probably run into SPI issues at higher speeds without proper termination even with relatively short cable length.
6) It dissipates 800mW at most in high-speed mode, so depends. If you're putting a too-high voltage on DVDD you might be frying the ADC.
 

Offline rsridharTopic starter

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #2 on: July 07, 2018, 07:03:20 pm »
1) Unless specified otherwise, they all need to be connected (to the right voltages respectively)
2) If you have a separate ground plane for analog and digital, tie them together at the ADC. It's a complicated topic, and usually fine to use the same ground unless you need the performance.
3) IOVDD needs to be within 1.65-3.6V, DVDD depends on the frequency you run the ADC at, check the datasheet.
  VCOM is an output pin for AVDD/2, VREFN/P is for connecting a reference voltage. Specifically, this ADC doesn't seem to have an internal reference, so connect it to an appropriate voltage reference (check data sheet).
4) You're not supposed to set DRDY low. DRDY is an output pin that indicates that a reading is available.
5) You'll probably run into SPI issues at higher speeds without proper termination even with relatively short cable length.
6) It dissipates 800mW at most in high-speed mode, so depends. If you're putting a too-high voltage on DVDD you might be frying the ADC.

Thanks, Ill make these fixes and see if I cant get this thing up and running!  Cheers!
 

Offline rsjsouza

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #3 on: July 09, 2018, 12:55:30 pm »
One additional detail: take a look at the development kit documentation for an example of a fully working PCB and electrical diagrams.
http://www.ti.com/tool/ADS1278EVM-PDK
Vbe - vídeo blog eletrônico http://videos.vbeletronico.com

Oh, the "whys" of the datasheets... The information is there not to be an axiomatic truth, but instead each speck of data must be slowly inhaled while carefully performing a deep search inside oneself to find the true metaphysical sense...
 

Offline james_s

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #4 on: July 12, 2018, 05:10:04 pm »
If it got so hot that it smells, then it is probably ruined. I would start by figuring out what you connected backwards or to the wrong voltage.
 

Offline rsridharTopic starter

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #5 on: July 14, 2018, 07:13:34 am »
If it got so hot that it smells, then it is probably ruined. I would start by figuring out what you connected backwards or to the wrong voltage.

I rewired it properly; got no more smell, but it also doesnt seem to work. I figured I mustve fried it.  Unfortunately the online store I used to buy the first is sold out; I ordered from another store and my package was lost, AND now the second store is sold out  |O
Hopefully itll turn up by next week.  Ill update this thread when it does...probably to ask for more help.

Im also trying to interface with an Analog Devices DAC:
http://www.analog.com/media/en/technical-documentation/data-sheets/AD1933.pdf

There are quite a few things that dont make sense to me here on this datasheet.  FIrst,  it mentions:
Quote
In addition, it is especially important
that the clock signal not be passed through an FPGA, CPLD, or
other large digital chip (such as a DSP) before being applied to
the AD1933. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals

Is this true?  Will I run into issues if my clock is generated by an fpga?

Secondly on the DAC, there are some points that I dont understand.  There are 4 inputs labeled:
Quote
DSATA4DACSerial Data Input 4. Input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX
DAC2 data out (to external DAC2).

DSATA3 - DAC Serial Data Input 3. Data input to DAC3 in/TDM DAC2 data in (dual-line mode)/AUX
not used.

DSATA2 - DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX not used.

DSATA1 -DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in.
 
Why does DSATA4 have so many purposes?  Generally, what do these channels do???  I assume they are (somehow) the channels we provide data to the DAC in; but in that case why are all their descriptions different?  Also, the datasheet doesnt have any timing diagrams of how to interface with the DAC.

Also the channels:
Quote
CIN - Control Data Input (SPI).
COUT - Control Data Output(SPI).

Do these somehow provide me access to the Control Registers, given on page 19 of the datasheet?

To be honest, this entire DAC datasheet has me lost about where to even begin...aside from the CIN/COUT diagrams, all the timing diagrams make reference to channels that dont exist (LRCLK, DATA) and terms like "slot 1 left 1" "Slot 1 right 1" which make no sense to me.

Table 11 also shows some differences between Stereo, TDM, and Aux modes.  What are these?

Any light anyone can shed on such a DAC - or any general guidelines - are much appreciated.  I know Im a complete beginner at this, so I apologize that my questions are probably so obvious.
« Last Edit: July 14, 2018, 07:19:41 am by rsridhar »
 

Offline iMo

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #6 on: July 18, 2018, 05:58:35 pm »
Would not be better to start small? With something you are better familiar with?
Interfacing the ads1278 with an FPGA could be an extremely difficult exercise if you were a beginner with this stuff..  ;)
Readers discretion is advised..
 

Offline james_s

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Re: Interfacing with TI ads1278 ADC with Cyclone IV FPGA
« Reply #7 on: July 18, 2018, 07:49:34 pm »
I had that thought too, but wasn't sure where the OP was in terms of FPGA development experience. I would certainly suggest starting with one of the small and inexpensive SPI, I2C or parallel ADCs and go from there.
 


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