ON and OFF Power Switching Circuit

[Praxian]

Hi

I'm looking to design a circuit that allows me to supply 12V power from a DC to DC inverter. The aim of the design circuit is to use as little power as possible whilst it is switched on. There will be an overall kill switch on the DC-DC converter that will be used when this circuit is not required for large periods of time, therefor a small amount of power use when this circuit is in an OFF state is acceptable as most of the time after engaging into the OFF state the converters kill switch will be turned OFF. There are a few requirements of the circuit though.

It needs one ON push button and two OFF push buttons that need to be wired up such that they are isolated from the circuit and are incapable of delivering more than 50mA of current. (The switches will be placed a few meters away from the circuit but cannot carry greater than 50mA of current due to regulations that apply to the design.

My designs so far for this are to use a high resistance to pull up the switches as seen in the attached images.
(The 1K resistors are placeholders until I calculate the optimal resistance)

I have a working design for the circuit however it  I have tried multiple ways of using the out signal with another MOSFET or two to latch the first P channel MOSFET on without any success.

I've looked at EEVblog's video: EEVblog #262 - World's Simplest Soft Latching Power Switch Circuit
https://youtu.be/Foc9R0dC2iI
However I'm unsure on how to do this in conjunction with the requirements of the switches and pulling them up.


Does anyone have any suggestions on how I could design this circuit?


Sorry if my explanation is confusing I'm a newbie to the forum.
Thanks in advanced.

[Cliff Matthews]

Question is confusing.. perhaps draw a complete idea. Was it a convertor or inverter? And the switch supplies current to it or from it?

[grifftech]

on button: push connectors together
off buttons: complicated mechanism to remove connector

[Ian.M]

Don't try to Muntz it.  You need a flipflop to latch the switches and you need something beefy to drive the MOSFET gate.  Both can be done with a CMOS 555.  The current consumption with no switch pressed will be fairly small, typically a few hundred uA.
 

N.B. MOSFET shown is for simulation only.  Pick one appropriate to the load current and with  sufficient Vds rating to handle any transients at switchoff.

The RC networks at the inputs are required for safety (no single part failure can allow more than 12mA to flow to the switches), glitch filtering and to guarantee it starts up OFF, which is why the caps return to different rails.

LTSPICE simulation attached. If you want tp see what happens if the switches are pressed at the same time, the simplest is to add a wire shorting them togeter or shorting one of them.

If you need lower idle current than that, you'll need to go to 4000 series CMOS, e.g. CD4011 quad NAND.  Wire it as a S-R NAND latch, with three gates paralleled for the side that drives the MOSFET gate.  Again use the resistors and capacitors I have used to filter glitches and provide a known switch-on state.

[hugo]

Take a look at this circuit, it can do 12V@1A, just pick up the right P channel MOSFET (Ids max,Vgs max) :

S1 ON
S2 OFF

[Ian.M]

Post the LTSPICE .asc file so the people taking a look at it can try it without having to redraw it.   How would you modify it to comply with the 50mA regulatory current limit to the switches?  Not only must it meed that limit for any conceivable single component failure (e.g. failed gate oxide in M1)  but SW1 charging C1 to ground the gate almost certainly transiently violates it out of the box!