Electronics > Beginners
is it fine to have floating pin with NE555 set for VCO
StillTrying:
--- Quote from: LaserTazerPhaser on September 21, 2019, 04:28:28 am ---An ne556 is ideal for this.
--- End quote ---
I've made a few attempts to completely separate the frequency and duty using a fast CMOS TC556. They weren't very good for the 1Hz to 2MHz range I was aiming for, but OK for frequency ranges up to about 100X. At mid frequencies 1% to 99% duty was possible, at MHz you're stuck with 40%-60% of adjustment.
https://www.eevblog.com/forum/projects/change-pulse-width-of-a-signal/msg1129000/#msg1129000
Gary350z:
--- Quote from: T3sl4co1l on September 21, 2019, 01:45:47 pm ---ESD of hazardous magnitude will damage it, regardless whether the transistor is on or off, or wired or not...
Tim
--- End quote ---
Question for Tim,
If you have a discrete small signal bipolar transistor wired up with full base drive, and an open collector, do you think a static discharge on the collector will destroy the transistor? I'm talking about an everyday static discharge, not like a 10 inch spark.
PS. I noticed your website at the bottom of your message, I'll have a look.
T3sl4co1l:
Diodes Inc. for example rates their MMBT3904 for 4kV HBM ESD.
https://www.diodes.com/assets/Datasheets/ds30036.pdf
Doesn't matter which combination of terminals, as far as I know.
Tim
Ian.M:
All BJT junctions will Zener or Avalanche under sufficient reverse voltage stress. Whether or not its destructive depends on a number of factors including pulse energy, how vulnerable the silicon structure is to hot-spotting, and if the peak emitter current is sufficient to fuse the bond-wire (as the collector is usually directly bonded to the tab or leadframe).
Its possible to get a rough idea of the currents and energies involved by SPICE modelling. I've attached a LTspice sim of a HBM discharge to the collector of a 2N3904. If you are interested in the reverse breakdown of the B-E and C-B junctions, the LTspice 2N3904 model has to be patched with realistic Vceo and reverse Vbe breakdown voltages as the standard.bjt library model doesn't specify them so defaults them to infinity.
N.B. Results are only as good as the transistor model used. As most published transistor models don't specify breakdown behaviour, simmed peak currents and pulse energies should be viewed with scepticism. I usually use this sim jig for evaluating theoretical designs of ESD protection networks to quickly eliminate obviously inadequate designs. Real world testing is still essential.
Gyro:
Instead of agonizing about it too much, wouldn't be easier just to decouple the discharge pin to ground with a cheap 100nF Y5U ceramic. That would be enough to absorb any reasonable ESD spike and leaky enough to prevent long term voltage buildup.
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