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Is it OK to cherrypick a portion of whole 74 series part in CPLD Quartus II ?

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james_s:
My comment was not to dismiss HDL, it's still the way to go. The schematic capture tool is a waste of time, it's a gimmick to show off in trade show demos, nobody actually uses it. I don't know why you are so averse to trying.

rstofer:

--- Quote from: james_s on December 15, 2019, 05:53:24 pm ---My comment was not to dismiss HDL, it's still the way to go. The schematic capture tool is a waste of time, it's a gimmick to show off in trade show demos, nobody actually uses it. I don't know why you are so averse to trying.

--- End quote ---

Especially since half of the logic is in 8:1 multiplexers which would be coded once as a component and simply instantiated 6 times with varying inputs and outputs.  There is a 3 bit counter which would look amazingly like the D-flop I posted above (except for incrementing a count), a quad latch which would instantiated 4 times and is nothing more than a wider version of the D-flop above and, finally, a 2:1 4-channel MUX.  I guess if I were to sit down to write, the entire thing would take less than an hour.  Two, at the most.  If I counted right, there are 4 components to create plus a top module to tie them together.  Yes, the constraints file will take time.  Probably more than it took to do the logic.

But the project works, so, by definition, it's ok.  If the OP prefers schematic entry, so be it.

In this particular case, the schematic is more understandable than the HDL.  It flows nicely from left to right, there's nothing tricky about how it works.  It's a pretty clean solution.

iMo:
Schematics capture is perfectly fine when you spent your life among 74xx packages.
It could be much faster than with hdl, especially when you are going to copy 1:1 an older design. The libraries (ie Xilinx ISE) include almost all you used to use decades back.

unitedatoms:
Great. Thank you for moral support. I have succeeded to the point when I can choose physical pins to schematics inputs and outputs.

In regards to readability of schematics. The muxes are just a lookup tables 1-bit wide. It is easy to slap a mux and hardwire the table of what you need to happen on every state of counter. Then I rely on minimizer, which will reduce the mux to few gates. The D-Flip-Flops are my intent to express to synthesizer, that certain intermediate values must be computed same time. I think. So if it takes more than one clock, I do not care, as long as result arrive coherent across several bits. And at the output I only care about ability to capture the data with external D-Flip-Flop to erase the jitter for analog reasons.

What was not possible in WinCUPL tool, that intermediate results had to be real physical pins. (or I did not understand something about Atmel CPLDs). That caused unnecessary outputs to appear involved on chip package. In Quartus, this was not a problem. The tool says that unused pins are forced to be outputs with logic 0 value all the time. I am grounding them with 50 Ohm resistors, just in case.

It is great to have such a powerful tools for free together with full 74 series library.

james_s:
CUPL is an ancient language used for PLDs, these are much older, more primitive parts compared to CPLDs in which the C stands for Complex. It's a limitation of the old PLDs that outputs need to be physical pins, they have no interconnect network, the datasheet for the parts shows how the internal logic is wired up.

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