Electronics > Beginners
Is it OK to cherrypick a portion of whole 74 series part in CPLD Quartus II ?
unitedatoms:
I am trying to learn how to use Altera Quartus II schematic entry to make simple CPLD for MAX7000A series chip. NOT using HDL, just using the schematic entry.
When I express my design using 74 logic series symbol from Maxplus2 library, I think that the symbol is a complete abstraction, representing an ideal function. So I take a larger part say 4-bit counter 74163 to implement a 3-bit counter and leave higher bit unused. The rest of unused pins go grounded or ties to logic 1 (VCC).
Question: Will Quartus figure out, that the intended function is simpler than library part, and will optimize out (remove) unnecessary nets and gates ?
Context: I am trying to develop a phase detector with 0.00x degree resolution at 10Hz..10MHz range using CPLD and FET switches. Based on old HP LCR meter from 1980s. The circuit is ECL Motorolla logic. Too difficult to attempt with my skills and today's parts. It has at leat 20 gates, flip-flops. So I think I need CMOS CPLD instead of ECL. I have modelled the digital circuit in Atmel CPLD tool and simulation worked OK. However there is no detailed timing report in Atmel tools. Only ideal 0 picosecond charts. I decided to try Intel (Altera) tools to see what CPLD can do at 80 MHz with picosecond reports, etc. And found that the best way to express logic is using symbols instead of HDL (for me personally).
james_s:
Anything that isn't actively used will get optimized out, it can actually be frustrating when developing a more complex project and a large part of the whole circuit gets optimized out. Usually because a clock or enable is omitted somewhere or not being driven.
The schematic entry is a waste of time though IMO, if your project only has 20 gates that should be trivial to do in VHDL or Verilog. You could pick up enough to code it at a gate level in an evening or two. I started out using the schematic entry in Quartus and later wished I had just skipped it or moved on after using it to make some trivially simple project to test my hardware. The result is proprietary non-portable code that is very hard to debug and maintain.
unitedatoms:
Great. Thank you. The HDL will come much later for me. I am trying to skip learning HDL if possible. That is different level. Also the libraries could be major problem with new language. Usually new language is not that difficult, but libraries can turn to be infinite and with no feel what there in libraries or in language is mainstream vs what is poorly made and abandoned and not maintained anymore.
james_s:
HDL has no concept of libraries, it is a standardized language used to describe digital logic. With HDL you are not writing a program, you are describing logic with a language that superficially resembles a program. Take a look at it, you might be pleasantly surprised. The closest thing to a library like the arduino sense will be another HDL file that can be instantiated into your project. It's not platform specific and doesn't get outdated.
D <= A AND B AND C;
That describes a 3 input AND gate in VHDL, pretty trivial. The signals can be named something more meaningful than single letters of course.
Free Range VHDL is a free e-book I found very helpful. I also gained a lot from experimenting with Grant Searle's Multicomp project.
rstofer:
For giggles, I coded up a D-flop with synchronous reset, synthesized it and copied the schematic. The BUF type things are buffers because it is assumed that, lacking any surrounding logic, these signal originate and terminate outside the chip.
--- Code: ---[font=courier]
entity D_flop is
Port ( D : in STD_LOGIC;
Q : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end D_flop;
architecture Behavioral of D_flop is
begin
process(clk)
begin
if rising_edge (clk) then
if reset = '1' then
Q <= '0'; -- synchronous reset
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
--- End code ---
[/font]
It doesn't get much easier than this! I attached the synthesized schematic. Note that I got just what I expected: A D-flop with synchronous reset.
The point of this exercise is simple: There are only a handful of common logic blocks (I'm going to ignore edge cases like DSP, SERDES and others). There is the basic MUX, decoder, counter, flop, register and discrete logic. Each of these are coded to a standard, they're always the same, reset is always the first test of a clocked process (and the D-flop is an example of a clocked process) and once that standard is understood, it's like playing with LEGO. Just pile up building blocks. Of course, the Finite State Machine is what makes it all play but, at its core, it is just another clocked process with a few more signals than the lowly D-flop. But they work the same! And just try to create an FSM with a schematic. It might be possible but it will darn sure be complicated. I can't even imagine what a FSM with 100+ states might look like!
It isn't a matter of code, that is pretty much standardized, it is tying the blocks together that makes a system. You're making a bigger deal out of HDL than it is. Every block has a coding standard (or at least 3 in the case of the MUX) and connecting them up with signals is no different than dealing in terms of wires.
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