Electronics > Beginners

Is it possible to route this in 4 layer 5cm x 5cm?

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soFPG:

--- Quote ---If you’re intending to have it automatically loaded
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No, I am doing this myself.

OwO:

--- Quote from: Yansi on December 01, 2019, 05:39:58 pm ---What pitch are these BGAs? If not 1mm, forget about making the PCBs in china  for dirt cheap.  0.8mm pitch BGA can be made successfully with a 0.25 drilled vias at maximum (or  maybe, seen them with .3mm drilled vias, while making sacrafices and bending the design rules a bit). Cheap chinese prototype pcbs end with .3mm drills.

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Incorrect. 0.8mm BGAs are officially supported by JLC on 4 layers and above with 0.2mm drills and 0.45mm annulus outer diameter. I have done plenty of boards with 0.8mm pitch BGA (Zynq, AD9363, DDR3 memory, etc) on JLC and had zero problems. See: https://github.com/gabriel-tenma-white/sdr5

ebclr:
Hi Grabriel on https://github.com/gabriel-tenma-white/sdr5 what is the PCB software used?

OwO:

--- Quote from: ebclr on December 02, 2019, 07:00:31 am ---Hi Grabriel on https://github.com/gabriel-tenma-white/sdr5 what is the PCB software used?

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gEDA PCB. I am using the original variant although there is a newer more actively developed fork that you might want to consider using: https://www.eevblog.com/forum/geda/pcb-rnd/

soFPG:

--- Quote from: OwO on December 02, 2019, 03:35:47 am ---Incorrect. 0.8mm BGAs are officially supported by JLC on 4 layers and above with 0.2mm drills and 0.45mm annulus outer diameter. I have done plenty of boards with 0.8mm pitch BGA (Zynq, AD9363, DDR3 memory, etc) on JLC and had zero problems. See: https://github.com/gabriel-tenma-white/sdr5

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Wow! This is a complex board in just 4 layers. Do you have any tips & tricks for me how to start routing this? I guess the most important traces are address- & databus, then power planes?

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