Electronics > Beginners
Is it possible to route this in 4 layer 5cm x 5cm?
Siwastaja:
Are your passives 0603? If yes, changing 'em all to 0402 is obvious with no downsides; consider 0201 in some critical places. Also make sure your footprint is the minimum possible and avoid excess courtyard.
Look if you can replace the largish XTAL with a smaller SMD package. You may need to pay some $0.20 more for such a miniatyre crystal, though.
Also look if your SOIC16 IC, or an alternative, is available in a smaller package. Often they are cheaper, as well.
Adding routing layers likely won't help make such a design smaller, as vias take space, so finding the smallest component footprints is the key.
Double-sided assembly is done all the time, but if you can do it in one layer, you save a bit on assembly cost. I'd try to do it on 1 layer, for such simple design.
AndyC_772:
No way that's a 4 layer board. The top layer is all components, 2 and 3 are your power and ground planes, which gives you one useful tracking layer.
The minimum number of layers may well be dictated by how many it takes to escape the BGA. Start by looking at that, work out what the track and via geometry needs to be in order to reach the innermost balls, then go from there.
I'd probably start with the assumption that it's an 8 layer board, and maybe perhaps drop down to 6 if it looks possible once I've made a good start on the design.
I'd also lay it out on a board whose shape is a better fit for the components, or the enclosure it needs to fit, or any criterion more important than an arbitrary price difference at a super cheap hobby PCB shop which almost certainly won't be able to fabricate the design anyway.
OwO:
Can you post a schematic? I usually start by planning and visualizing the overall layout of the major components (e.g. Zynq in the middle, DDR3 chips on the left, analog stuff on the right, etc) taking into account the pinout of the chips. Next I think about where data busses are and how they can be allocated to layers taking into account signal integrity.
Power planes are undesirable on a 4 layer board because you have to stitch it to the ground plane with capacitors regularly since the planes are distant. Better to use power traces which makes it easier to simulate as well. I don't know why people keep implying you have to have power planes but I think it's bad advice and a waste of layers, and the people bringing this up also tend to be the ones that need 8-12 layers to do something that would take me 4 layers. Signal integrity is not hard as some would imply, and in my design the DDR3 interface has plenty of eye opening at max speed (wider eye than everyone else that posted on Xilinx forums, which is also a place where everyone says you need 10 layers for Zynq + DDR).
For critical signals (e.g. DDR) you have two signal layers to work with, and the other two layers must be ground or power in the area directly above and below the signal traces; in my case the stackup in the DDR area is: traces, ground, traces, VCCDDR plane. The VCCDDR plane only exists in that area, and the only reason for it is that VCCDDR would be hard to route otherwise (it has to be brought to many pins of the DDR chips and the Zynq), and it doubles as a "ground" plane for the DDR signals. Everywhere else on the board that layer is a simple ground plane with a few traces. in1 (first layer below top) is the dedicated, unbroken ground plane layer. Of course, these "rules" are all broken in the RF area of the board where signals go in striplines surrounded by via stitched "boxes", and which layers this happens on is completely inconsequential as long as you stitched everything properly.
soFPG:
--- Quote ---I'd probably start with the assumption that it's an 8 layer board
--- End quote ---
I agree with you if we are talking from my level of skill in PCB layout at the moment. But I have seen PC-motherboards with dual XEON CPUs + a lot of DDR3-Banks + southbridge + PCIe done on 8 layers. So no way there is a need for 8 layers (if it is done correct).
I am going to place the caps on the bottom side and try to re-arrange things and learn the routing part while I am doing it (I guess).
--- Quote --- or any criterion more important than an arbitrary price difference at a super cheap hobby PCB shop which almost certainly won't be able to fabricate the design anyway.
--- End quote ---
There are some YouTube videos out there with FPGA + high speed DDR-RAM manufactured by JLCPCB and @OwO just posted a link to his design.
--- Quote ---Are your passives 0603?
--- End quote ---
They are 0805 :-\ But I will probably switch them for 0603 and 0402. 0201 is too small for me even if I just have to place it on the pads and not soldering it (which is done by the oven).
EEVblog:
--- Quote from: soFPG on December 01, 2019, 05:47:27 pm ---Those are 0.8mm BGAs.
And JLCPCB lists 0.2mm as min via hole size: https://jlcpcb.com/capabilities/Capabilities
--- End quote ---
Don't forget the 0.45mm minimum via diameter
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