Electronics > Beginners

Is it possible to route this in 4 layer 5cm x 5cm?

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EEVblog:

--- Quote from: soFPG on December 01, 2019, 05:34:43 pm ---I never did a board with more than 4 layers and this is my first attempt and in general I am not very experienced in routing PCBs.

--- End quote ---



Heaps of room.
First thing is to look at your passives and optimise them in several ways:
1) Do you actually need every single one of them?
2) Can you use a smaller package size?
3) Can you use a smaller pad shape?
4) Can they go on the bottom for a double sided load?

Siwastaja:
0805 is just ridiculous.

rstofer:
Don't forget that it is fair to scramble address and data lines.  So what if the array isn't linearly addressed or the bits aren't stored in order from high to low.

Using an FPGA gives you a lot of flexibility in pin assignment.

I would work to simplify the lower right rat's nest first.

Yansi:
But not that fast with address scrambling!

Data lines may be swapped only within respective byte lanes (if the memory has any used) and with SDRAM, address lines can't be scrambled, due to them serving as a command transmission bus to the memory chips.

TomS_:

--- Quote from: soFPG on December 01, 2019, 06:55:58 pm ---I don't know if it is possible to do a oven-reflow of a PCB populated on both sides? If I only put lightweight caps on the bottom layer I could probably reflow them first and then do the top side while the components on the bottom side are taped with kapton?

--- End quote ---

I have seen some people suggest using a solder with a higher melting temperature for the first side/load, such that when flipped over and reflowed for the other side using a solder with a lower melting point, the first side ideally doesnt melt and everything stays in place.

Otherwise, you can probably help your layout a bit if, for example, you disregard the order of the address and data lines of the SRAM chip. Assign them according to what is easiest to route, since it doesnt particularly matter what order the bits are stored, and jumbled up address lines just results in data being written all over the chip.

The flash chip will need more attention to in-order data and address signals, unless you write some tools to slice up your resulting binary image and jumble it around to suit - it has been done before! check out mikeselectricstuff on YouTube where he talks about a printer buffer he designed and used that very technique.

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