Can you post a schematic? I usually start by planning and visualizing the overall layout of the major components (e.g. Zynq in the middle, DDR3 chips on the left, analog stuff on the right, etc) taking into account the pinout of the chips. Next I think about where data busses are and how they can be allocated to layers taking into account signal integrity.
Power planes are undesirable on a 4 layer board because you have to stitch it to the ground plane with capacitors regularly since the planes are distant. Better to use power traces which makes it easier to simulate as well. I don't know why people keep implying you have to have power planes but I think it's bad advice and a waste of layers, and the people bringing this up also tend to be the ones that need 8-12 layers to do something that would take me 4 layers. Signal integrity is not hard as some would imply, and in my design the DDR3 interface has plenty of eye opening at max speed (wider eye than everyone else that posted on Xilinx forums, which is also a place where everyone says you need 10 layers for Zynq + DDR).
For critical signals (e.g. DDR) you have two signal layers to work with, and the other two layers must be ground or power in the area directly above and below the signal traces; in my case the stackup in the DDR area is: traces, ground, traces, VCCDDR plane. The VCCDDR plane only exists in that area, and the only reason for it is that VCCDDR would be hard to route otherwise (it has to be brought to many pins of the DDR chips and the Zynq), and it doubles as a "ground" plane for the DDR signals. Everywhere else on the board that layer is a simple ground plane with a few traces. in1 (first layer below top) is the dedicated, unbroken ground plane layer. Of course, these "rules" are all broken in the RF area of the board where signals go in striplines surrounded by via stitched "boxes", and which layers this happens on is completely inconsequential as long as you stitched everything properly.