Author Topic: Is it possible to route this in 4 layer 5cm x 5cm?  (Read 1700 times)

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Offline soFPG

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Is it possible to route this in 4 layer 5cm x 5cm?
« on: December 01, 2019, 05:34:43 pm »
I never did a board with more than 4 layers and this is my first attempt and in general I am not very experienced in routing PCBs.

At JLCPCB a 4 layer 50mm x 50mm PCB is very cheap but as soon as the area goes above 50mm x 50mm it doubles in price - so it would be nice to get everything into this 5cm square.
But - maybe there is no way fitting every component? What do the PCB routing experts here say - is it possible (given JLCPCB capabilities of 3.5mil traces/clearance, 0.2mm via holes)?

It looks close to impossible to me especially that a lot of connections from the big BGA to the TSSOP and the other BGA should be matched regarding length.

My approach would be routing it like this and if it doesn't work out somehow re-arrange the components and then try again.
 

Online Yansi

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #1 on: December 01, 2019, 05:39:58 pm »
Why do you take a double-BGA high speed digital board as you first 4layer trial?

What pitch are these BGAs? If not 1mm, forget about making the PCBs in china  for dirt cheap.  0.8mm pitch BGA can be made successfully with a 0.25 drilled vias at maximum (or  maybe, seen them with .3mm drilled vias, while making sacrafices and bending the design rules a bit). Cheap chinese prototype pcbs end with .3mm drills.
« Last Edit: December 01, 2019, 05:42:26 pm by Yansi »
 
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Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #2 on: December 01, 2019, 05:47:27 pm »
Those are 0.8mm BGAs.

And JLCPCB lists 0.2mm as min via hole size: https://jlcpcb.com/capabilities/Capabilities

Edit: This is not very high speed. The TSSOP package is SRAM (12ns access time - so 80MHz) and the other BGA is NOR-Flash.
« Last Edit: December 01, 2019, 05:50:52 pm by soFPG »
 

Offline Howardlong

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #3 on: December 01, 2019, 05:55:10 pm »
Look at

o using 0402 passives (or smaller) unless there’s a reason to use larger;
o double sided load;
o starting with something a lot less ambitious, or get someone a lot more experienced to do it for you.

 

Offline ebclr

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #4 on: December 01, 2019, 05:59:27 pm »
You can get some extra spaces, putting some components on the other side of the board, using the 2 faces, have more room to save space


By the way, is an FPGA, Memory, USB convert for jtag , or something like this?
 

Offline jhpadjustable

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #5 on: December 01, 2019, 06:33:07 pm »
What other people said, plus, think of all the space you'll get back with a .050" pitch JTAG connector. Or maybe use FFC connectors for everything instead.
"There are more things in heaven and earth, Arduino, than are dreamt of in your philosophy."
 

Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #6 on: December 01, 2019, 06:55:58 pm »
Quote
You can get some extra spaces, putting some components on the other side of the board, using the 2 faces, have more room to save space
I don't know if it is possible to do a oven-reflow of a PCB populated on both sides? If I only put lightweight caps on the bottom layer I could probably reflow them first and then do the top side while the components on the bottom side are taped with kapton?

Quote
By the way, is an FPGA, Memory, USB convert for jtag , or something like this?
This is a ARM7TDMI-based CPU with external SRAM and flash. Then there is a UART/USB converter (CH340G) to program the internal SRAM.

Quote
think of all the space you'll get back with a .050" pitch JTAG connector.
My plan is to use the Jlink EDU as a JTAG debugger and as far as I remember it only has a 0.1" connector.

Quote
Or maybe use FFC connectors for everything instead.
Don't know how that would work for UART and stuff? The 50-pin ZIF connector is used to connect an external display
« Last Edit: December 01, 2019, 06:58:05 pm by soFPG »
 

Offline langwadt

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #7 on: December 01, 2019, 07:06:15 pm »
Quote
You can get some extra spaces, putting some components on the other side of the board, using the 2 faces, have more room to save space
I don't know if it is possible to do a oven-reflow of a PCB populated on both sides? If I only put lightweight caps on the bottom layer I could probably reflow them first and then do the top side while the components on the bottom side are taped with kapton?

Quote
think of all the space you'll get back with a .050" pitch JTAG connector.
My plan is to use the Jlink EDU as a JTAG debugger and as far as I remember it only has a 0.1" connector.


double sided mounting is done all the time, small parts are held on by the surface tension of the solder only big parts need glue

you can use any connector or even test points and pogo pins for JTAG, just make a cable to fit

 

Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #8 on: December 01, 2019, 07:13:33 pm »
Quote
you can use any connector or even test points and pogo pins for JTAG, just make a cable to fit
I thought it would be nice to have a fitting receptacle, but you are probably right.

Putting caps on the bottom is definitely a thing I am going to consider.
 

Offline blueskull

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #9 on: December 01, 2019, 07:14:49 pm »
This is what I did recently. 35mm*17mm, with a large QFN FPGA and two small QFNs, both 0.4mm pitch, plus a 0.5mm pitch DFN and a bit short of 100 passives.

882864-0

Doable? Yes. Pleasant? No. BTW, this has been fabricated by JLCPCB. It violated their 5 mil via to trace rule, but their CAM engineers were able to shave off some copper automatically to create non circle pads to fit in their rule, which Altium can't.

The board works, and I'm working on rev 2 with a few non critical features removed and some other features added, plus this time I will try to strictly stick to their design rules.

A bit of suggestion: hide all major voltage rails and ground in fly wire mode, so you can focus better on critical traces. This accelerates my workflow by quite a margin.
 
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Offline Howardlong

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #10 on: December 01, 2019, 07:31:52 pm »
If you’re intending to have it automatically loaded, you’ll need fiducial points too on both sides.
 

Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #11 on: December 01, 2019, 07:44:55 pm »
Quote
If you’re intending to have it automatically loaded
No, I am doing this myself.
 

Online OwO

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #12 on: December 02, 2019, 03:35:47 am »
What pitch are these BGAs? If not 1mm, forget about making the PCBs in china  for dirt cheap.  0.8mm pitch BGA can be made successfully with a 0.25 drilled vias at maximum (or  maybe, seen them with .3mm drilled vias, while making sacrafices and bending the design rules a bit). Cheap chinese prototype pcbs end with .3mm drills.

Incorrect. 0.8mm BGAs are officially supported by JLC on 4 layers and above with 0.2mm drills and 0.45mm annulus outer diameter. I have done plenty of boards with 0.8mm pitch BGA (Zynq, AD9363, DDR3 memory, etc) on JLC and had zero problems. See: https://github.com/gabriel-tenma-white/sdr5
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Offline ebclr

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #13 on: December 02, 2019, 07:00:31 am »
Hi Grabriel on https://github.com/gabriel-tenma-white/sdr5 what is the PCB software used?
 

Online OwO

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #14 on: December 02, 2019, 07:37:11 am »
Hi Grabriel on https://github.com/gabriel-tenma-white/sdr5 what is the PCB software used?

gEDA PCB. I am using the original variant although there is a newer more actively developed fork that you might want to consider using: https://www.eevblog.com/forum/geda/pcb-rnd/
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Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #15 on: December 02, 2019, 08:18:00 am »
Incorrect. 0.8mm BGAs are officially supported by JLC on 4 layers and above with 0.2mm drills and 0.45mm annulus outer diameter. I have done plenty of boards with 0.8mm pitch BGA (Zynq, AD9363, DDR3 memory, etc) on JLC and had zero problems. See: https://github.com/gabriel-tenma-white/sdr5

Wow! This is a complex board in just 4 layers. Do you have any tips & tricks for me how to start routing this? I guess the most important traces are address- & databus, then power planes?
 

Online Siwastaja

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #16 on: December 02, 2019, 08:20:13 am »
Are your passives 0603? If yes, changing 'em all to 0402 is obvious with no downsides; consider 0201 in some critical places. Also make sure your footprint is the minimum possible and avoid excess courtyard.

Look if you can replace the largish XTAL with a smaller SMD package. You may need to pay some $0.20 more for such a miniatyre crystal, though.

Also look if your SOIC16 IC, or an alternative, is available in a smaller package. Often they are cheaper, as well.

Adding routing layers likely won't help make such a design smaller, as vias take space, so finding the smallest component footprints is the key.

Double-sided assembly is done all the time, but if you can do it in one layer, you save a bit on assembly cost. I'd try to do it on 1 layer, for such simple design.
« Last Edit: December 02, 2019, 08:23:48 am by Siwastaja »
 
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Offline AndyC_772

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #17 on: December 02, 2019, 09:17:03 am »
No way that's a 4 layer board. The top layer is all components, 2 and 3 are your power and ground planes, which gives you one useful tracking layer.

The minimum number of layers may well be dictated by how many it takes to escape the BGA. Start by looking at that, work out what the track and via geometry needs to be in order to reach the innermost balls, then go from there.

I'd probably start with the assumption that it's an 8 layer board, and maybe perhaps drop down to 6 if it looks possible once I've made a good start on the design.

I'd also lay it out on a board whose shape is a better fit for the components, or the enclosure it needs to fit, or any criterion more important than an arbitrary price difference at a super cheap hobby PCB shop which almost certainly won't be able to fabricate the design anyway.

Online OwO

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #18 on: December 02, 2019, 10:20:10 am »
Can you post a schematic? I usually start by planning and visualizing the overall layout of the major components (e.g. Zynq in the middle, DDR3 chips on the left, analog stuff on the right, etc) taking into account the pinout of the chips. Next I think about where data busses are and how they can be allocated to layers taking into account signal integrity.

Power planes are undesirable on a 4 layer board because you have to stitch it to the ground plane with capacitors regularly since the planes are distant. Better to use power traces which makes it easier to simulate as well. I don't know why people keep implying you have to have power planes but I think it's bad advice and a waste of layers, and the people bringing this up also tend to be the ones that need 8-12 layers to do something that would take me 4 layers. Signal integrity is not hard as some would imply, and in my design the DDR3 interface has plenty of eye opening at max speed (wider eye than everyone else that posted on Xilinx forums, which is also a place where everyone says you need 10 layers for Zynq + DDR).

For critical signals (e.g. DDR) you have two signal layers to work with, and the other two layers must be ground or power in the area directly above and below the signal traces; in my case the stackup in the DDR area is: traces, ground, traces, VCCDDR plane. The VCCDDR plane only exists in that area, and the only reason for it is that VCCDDR would be hard to route otherwise (it has to be brought to many pins of the DDR chips and the Zynq), and it doubles as a "ground" plane for the DDR signals. Everywhere else on the board that layer is a simple ground plane with a few traces. in1 (first layer below top) is the dedicated, unbroken ground plane layer. Of course, these "rules" are all broken in the RF area of the board where signals go in striplines surrounded by via stitched "boxes", and which layers this happens on is completely inconsequential as long as you stitched everything properly.
« Last Edit: December 02, 2019, 10:23:59 am by OwO »
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Offline soFPG

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #19 on: December 02, 2019, 10:25:41 am »
Quote
I'd probably start with the assumption that it's an 8 layer board
I agree with you if we are talking from my level of skill in PCB layout at the moment. But I have seen PC-motherboards with dual XEON CPUs + a lot of DDR3-Banks + southbridge + PCIe done on 8 layers. So no way there is a need for 8 layers (if it is done correct).
I am going to place the caps on the bottom side and try to re-arrange things and learn the routing part while I am doing it (I guess).

Quote
or any criterion more important than an arbitrary price difference at a super cheap hobby PCB shop which almost certainly won't be able to fabricate the design anyway.
There are some YouTube videos out there with FPGA + high speed DDR-RAM manufactured by JLCPCB and @OwO just posted a link to his design.

Quote
Are your passives 0603?
They are 0805  :-\ But I will probably switch them for 0603 and 0402. 0201 is too small for me even if I just have to place it on the pads and not soldering it (which is done by the oven).

 

Offline EEVblog

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #20 on: December 02, 2019, 10:34:22 am »
Those are 0.8mm BGAs.
And JLCPCB lists 0.2mm as min via hole size: https://jlcpcb.com/capabilities/Capabilities

Don't forget the 0.45mm minimum via diameter
 

Offline EEVblog

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #21 on: December 02, 2019, 10:39:53 am »
I never did a board with more than 4 layers and this is my first attempt and in general I am not very experienced in routing PCBs.



Heaps of room.
First thing is to look at your passives and optimise them in several ways:
1) Do you actually need every single one of them?
2) Can you use a smaller package size?
3) Can you use a smaller pad shape?
4) Can they go on the bottom for a double sided load?
 

Online Siwastaja

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #22 on: December 02, 2019, 10:55:44 am »
0805 is just ridiculous.
 

Offline rstofer

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #23 on: December 02, 2019, 02:45:43 pm »
Don't forget that it is fair to scramble address and data lines.  So what if the array isn't linearly addressed or the bits aren't stored in order from high to low.

Using an FPGA gives you a lot of flexibility in pin assignment.

I would work to simplify the lower right rat's nest first.
 

Online Yansi

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Re: Is it possible to route this in 4 layer 5cm x 5cm?
« Reply #24 on: December 02, 2019, 03:03:30 pm »
But not that fast with address scrambling!

Data lines may be swapped only within respective byte lanes (if the memory has any used) and with SDRAM, address lines can't be scrambled, due to them serving as a command transmission bus to the memory chips.
 


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