Why would a 1.25 MSPS ADC have a 15 kHz LPF?

[SaintGimp]

I'm building a device to measure frequency content of a radio signal from 10 kHz to 100 kHz for a scientific application, but I'm not an expert in ADCs.  I'm trying to select an ADC to digitize the output from my amplifier stage so I can run an FFT on it.  I happened to look at the ADS8661 ADC from TI: https://www.ti.com/lit/ds/symlink/ads8665.pdf.  It's able to sample at 1.25 megasamples per second, which sounds fine, but it has an integrated 15 kHz second-order low pass filter in its front end.  I think that makes it unsuitable for my purpose but it left me wondering: why would you need a 1.25 MSPS ADC if you're so drastically limited in input bandwidth?  I mean, obviously it's useful to people, otherwise TI wouldn't make it, but I'm not sure what kinds of applications I'd chose this ADC for.  Can anyone enlighten me?

(EDIT) And can anyone suggest a suitable part for my application (digitizing a signal in order to do an FFT analysis up to 100 kHz)?

[ataradov]

My best guess - it is just a second order filer, and its performance is not that great. So they want to be able to capture as much unaliased signal as possible to do further digital filtering. They expect this device to work without external filtering.

[T3sl4co1l]

Who knows. Probably some custom design, then decided to sell it publicly after whatever contract period was up?

Also, watch out for sigma-delta ADCs, which only use one bit, and get the rest of the way with generous oversampling.  Technically, the sample rate is quite high, but the accuracy (ENOB) depends on bandwidth.  They're typically used for high accuracy at low bandwidth (16b+, 100s Hz), so yeah.

As for something good, many MCUs will have something suitable, or these seem likely:
https://www.digikey.com/short/vth2429d
The AD7276 looks quite good for as few pins as it is, and the prices go up from there.  None of the prices are all that great, with this AD part of all things being at the bottom...(AD tends to be expensive, but worthwhile?).

You'll need quite a bit of programming to get there, however you do it... plus you still need to get it back to whatever the rest of your acquisition system is.  So, I don't feel bad suggesting an MCU...

You may also wish to consider something more direct, like an SDR (software defined radio), or video capture something or other -- I'm not sure about the latter, but many things these days are little more than an ADC or DAC bolted to a high-speed port (USB2+, etc.), and the rest is solved in software, at great expense to CPU time (which, however, is extremely abundant these days, so it works).

An example that comes to mind is a USB-VGA dongle that turns out to be merely a three-channel DAC, streaming samples from a frame buffer; they've been repurposed for SDR (transmitter) use, even at rather high frequencies (possible thanks to the fast output transition times -- the pixel clock might only be 100 or 200MHz but the harmonics alias much higher, so, stick a wire in the output and you can literally chat on 900MHz with it, neato).

Afraid I know very little about these sort of dongles (above example excepted heh); I forget if the usual SDR modules have much if any input filtering/tuning or if they're basically a naked ADC, and likewise for video capture devices.  But they're probably worth a look.

Oh, and good old fashioned oscilloscopes, of course.  Plenty of those available with low sample rates (low for scopes is ~10M) and PC interfaces.

Mind, the one thing you'll likely miss with these (SDR, video capture, scope), is ENOB.  Video and scope don't really care either way (8 bits is about good enough), but SDR makes it back on filtering.  Basically, if you don't need much dynamic range, you're fine as well, but if you're hunting for weak harmonics or noise or whatever, you'll need whatever you need.

Tim

[radiolistener]

but it left me wondering: why would you need a 1.25 MSPS ADC if you're so drastically limited in input bandwidth?

Such LPF is needed to eliminate aliases due to frequency folding during discretization on ADC. Usually for a good alias rejection for 8 bit ADC the filter should be about 10 times narrow bandwidth than ADC sample rate, for 1.25 MS/s it should be about 125 kHz.

Probably there is more narrow bandwidth due to higher dynamic range of 12 bit ADC, so LPF needs to provide high enough attenuation for a frequencies outside ADC bandwidth.

[RoGeorge]

I think the clue for why the input filter is at a much lower frequency than expected (judging by the sample rate) is at page 56 of 71 https://www.ti.com/lit/ds/symlink/ads8665.pdf

The chip has galvanic isolation between the analog front end and the digital outputs.  This galvanic isolation barrier is inside the chip, can withstand hundreds to thousand of volts as a DC bias in the measured signal, but the crosstalk in terms of AC is too big at higher than 15kHz.  A 30kSa/s would be enough, but most probably they just reused an existing design of SAR, probably the lowest sample rate suited to fit in that ADC was a 1.25MSa/s SAR.

[Siwastaja]

This is in the core of basics of basics. It's taught pretty well on introductory university classes in signal processing, but somehow it's lost from general consciousness.

The fact is that 1.25MSPS ADC aliases any signal exceeding 625kHz. For example, a signal at 626kHz falsely seems like a 1kHz signal, which is obviously unacceptable, and you can't know if this is "real" 1kHz or aliased 1kHz signal.

There are only two solutions to the problem:
* Require the user to input signals that simply do not have such components to begin with (leaving only noise aliasing, but that might not be a problem)
* Filter anything above 625kHz with analog LPF.

Now it turns out, creating a brickwall analog filter that cuts of everything above 625kHz yet passes as high as, say, 600kHz, is really difficult to design, and at least very costly. At very high orders, number of opamps explodes, noise is added, passive tolerances start to matter, and so on.

On the other hand, digitally it's utterly trivial to design a near brickwall steep filter. Modern $2 microcontroller has enough processing power to run that FIR with gives perfectly uniform group delay, so little quantization noise that it can be considered ideal, and so on.

ADCs are also quite cheap nowadays. You can get a 3MSPS ADC for basically the same price as similarly performing 0.5MSPS.

So how did they end up with their design? Let me guess how the process went:

They needed 15kHz BW. That was the original requirement.

Then they specified some required out-band attenuation value, like say -60dB. Some understanding of the operation environment is needed; are there strong out-band interfering signals, or just some minor noise coupling from switchers?

Then they chose 2nd order LPF because really, that's what makes sense in such analog circuits (for really low cost stuff, 1st order RC would be used instead). When ADCs and processing was more expensive, a 4th or 6th order analog filter would have been economically viable. After all, this is about finding minimum in cost or complexity; steeper analog filter eases the role of ADC + processing, and vice versa.

Now, by using -12dB/oct filter, we can see -60dB is reached after 5 octaves, i.e., at 15kHz * 2^5 = 480kHz -> pick at least 960kHz ADC per Nyquist theorem. 1.25MSPS would have been the next available part.

Then, as final step, implement digital FIR or IIR filter with transition band at e.g. between 15kHz and 18kHz, then decimate to at least 18kHz*2 = 36ksmps, again per Nyquist theorem, to save storage memory without losing any information. Practically, decimating from 1.25MSPS with integer ratio of 32 would do it.

Or maybe they did not actually implement the digital filter and decimation step but leave it for the user to do, but in any case, this is the logical thinking behind why the ADC is so much higher rate than the input BW: to prevent aliasing, with lower cost and better performance of digital filters, avoiding analog filters.

Another side effect here is that the effective ADC resolution is increased and noise decreased because of oversampling. To construct one output sample at lower output BW, large number of input samples were used.

[T3sl4co1l]

I think the clue for why the input filter is at a much lower frequency than expected (judging by the sample rate) is at page 56 of 71 https://www.ti.com/lit/ds/symlink/ads8665.pdf

The chip has galvanic isolation between the analog front end and the digital outputs.  This galvanic isolation barrier is inside the chip, can withstand hundreds to thousand of volts as a DC bias in the measured signal, but the crosstalk in terms of AC is too big at higher than 15kHz.  A 30kSa/s would be enough, but most probably they just reused an existing design of SAR, probably the lowest sample rate suited to fit in that ADC was a 1.25MSa/s SAR.

Nah, that's just an application circuit.  Note on the next page they recommend SN6501, ISO7640 and etc. -- support components.  Abs. max. says +/-0.3V between grounds, nothing suspicious about the supplies, etc.

It does have an unusually high input voltage range of +/-15 or 20V, along with the filter; this sounds like a BOM reduction thing, so you just need to add ESD/surge protection (or use what's internal, offering a modest 4kV HBM), saving all the clamping and filtering components -- but only if your application happens to need exactly that bandwidth.

There are a few isolated ADCs out there, too -- they (manufacturers more generally) have integrated a number of things with their isolators, including DC-DC converters too(!).  This isn't one of them, but when you need one, they're pretty cool to have!

Tim

[David Hess]

The included low pass filter is because it is intended for applications below a couple kHz.  The 1.25 MSample/second maximum sampling rate just represents the maximum given the 250 nanosecond minimum acquisition time and 550 nanosecond maximum conversion time.

I think the clue for why the input filter is at a much lower frequency than expected (judging by the sample rate) is at page 56 of 71 https://www.ti.com/lit/ds/symlink/ads8665.pdf

The chip has galvanic isolation between the analog front end and the digital outputs.  This galvanic isolation barrier is inside the chip, can withstand hundreds to thousand of volts as a DC bias in the measured signal, but the crosstalk in terms of AC is too big at higher than 15kHz.  A 30kSa/s would be enough, but most probably they just reused an existing design of SAR, probably the lowest sample rate suited to fit in that ADC was a 1.25MSa/s SAR.

That is just an application example of how to build a galvanically isolated data acquisition system using the ADS8661.  By itself it has no isolation.