There are a few things I don't understand though. First, to verify my understanding is correct: using an enhancement mode N-MOSFET, the gate would be connected to VDD (1.8V in this case), the drain (I'm assuming) would be the new high-voltage-capable OD output, and the source would be connected to the MCU pin.
Correct.

When the MCU pin is pulled to ground, wouldn't the drain and source (which would be the MCU pin that the MCU is pulling to ground) be connected? If the drain is connected to an external device with, say, a 3.3V pull-up, the MCU pin is going to have to sink that current. How does this avoid the voltage limitation of the MCU pin?
Also, if the MCU pin is OD, that means the source would be floating sometimes (half the time in this case). Is there the same problem with this as there is with a floating gate?
This avoids the limitation, because the drain and source aren't unconditionally connected. The transistor still transists.

Note that, as the MCU pin turns off, source voltage rises -- pulled up by drain current. Which means Vgs is falling, which means at some point, drain current will also fall. When it falls below cutoff, the source stops rising, and the transistor is off.
You could add a small G-S pullup to ensure a valid logic level, true. The source isn't quite floating, as it's guaranteed between VDD-Vgs(th) and VDD+0.5 or so. Which is likely a valid logic level to the PIC as well, if that matters.
Which if you aren't aware -- it can be helpful to bias unused input pins to valid levels, or set them as outputs. Every logic input pin has a pair of transistors sensing that voltage, and if the voltage is inbetween valid logic thresholds, it can do annoying things, like draw more supply current (which might only be ~uA, but that can be significant in a battery powered device), or do weird instability things (oscillate, be sensitive to interference?). So it can be nice to have some pullup even if the pin level isn't otherwise important.
Some MCUs may have output-only pins, or input stages that can be completely disconnected, where this may not apply. Usually they are of the above (GPIO) type.
With the cascode option, would it be OK to rely on the current clamping mechanism that I think the PIC has on its GPIO pins (will verify first)? The short circuit thing should never happen; I brought that up as a "just in case" failsafe because I know MOSFETs can fail violently when pushed beyond spec.
Yes, if that's a thing it does then the current will be passed on perfectly through the cascode. Just make sure the power dissipation is acceptable and it should survive.
Which, if it's not -- you can implement other current limiting very simply in this configuration. Introduce a resistor between pin and source. Now the transistor can deliver an absolute maximum of (VDD-Vgs(on)) / Rs, with a saturation voltage around VDD-Vgs(on).
Note I say Vgs(on) instead of Vgs(th), because the "on" condition is at whatever Id is flowing; Vgs(th) is specified at, whatever it says, 50uA or the like. Use the transfer curve (Id as a function of Vgs) to estimate this.
This is better with BJTs, because you can make the offset voltage smaller, a Vbe (~0.7V) or even less.
Put another way: the current-limiting resistor is in series with the load, at low currents. So some saturation voltage is eaten up by it.
When I'm not pressed for layout space, I like to use BJTs like so:

For open-drain (well, open-collector in this case), you'd the bottom half, getting rid of R89, 90, 96 and Q7.
This also shows some EMI filtering and ESD protection. I find the FB + C does a nice job of smoothing out the rough edges from the logic signal, while the diode clamps ESD.
Some resistance between the ESD clamp and logic pin is generally recommended. Here, the base resistors provide that, so the driving source is well protected. The BJTs themselves can be pulled beyond the rails a fair ways without damage, they'll just zener into the emitter resistors.
A similar circuit using MOSFETs, you'd probably use directly grounded sources (rather than source degeneration resistors), and set the gate voltage carefully instead (e.g. a MOSFET current mirror -- bloody difficult to do with discrete transistors, basically an IC-only trick). In that case the body diodes serve as additional clamping, and maybe 10-100 ohms would be recommended, between the ESD diode and transistors.
If you don't necessarily have a higher voltage supply (as is the case for open-drain signals), use a zener or (unidirectional) TVS from GND to OUT, instead of the double diode.
Tim