Having been on a company tour at a facility that focuses on ESD protective IP blocks I thought this might be a good place to shared what I have learned/heard there. Some of this stuff will likely be obvious, others I might have misinterpreted/misheard, but here goes anyways:
There are three main models for ESD:
- Human Body Model (HBM): A person acts as a capacitor with a relatively large (few kOhms IIRC) resistance.
- Machine Model (MM): Smaller capacitance as the HBM, but no resistance (machines are usually made out of metals and/or other conductive materials)
- Charged Device Model (CDM): Charge is accumulated within/on the device itself. The charge is dissipated as soon as one of the pins finds a path to ground. I don't know if this is very common still, but the model was designed back when DIP packages were common in pick and place machines, and the machine vibrated them inside tubes. As soon as the device contacted any metal, it discharged potentially ruining your device.
*The ones we actually come in contact with most is similar to the HBM model. Usually we are dealing with a few KV of potential buildup, ratings go up to 20kV or even 50kV (important for situations where you have exposed contacts on a consumer product, like bus connectors, headphone jacks, ...). Discharge times are on the order of hundreds of nanoseconds (compared to a tens nanoseconds in the MN and sub-nanosecond pulses in the CDM models).
I was told that in "the olden days" (I'm 21 years old and thus haven't a clue if this is correct - feel free to point out any bs written here) ESD was a lot less of an issue. Discretes are less sensitive to ESD because the length of leads and the amount of PCB tracks alone form enough of an inductor to stop a lot of the current spikes. They are built at larger scales with thicker insulating layers and more surface area to dissipate the energy over. And the components were usually designed with higher voltages to begin with.
ESD becomes a more significant issue as you move down process nodes. A bigger FET, rated for higher voltage operation has a lot more space to dissipate the energy provided by the ESD. I don't remember exact numbers, but the oxide layer in 18nm FETs will have to deal with 50MV/cm (since they are so thin) during normal operation (1-3 volts DC). if they are hit by an ESD discharge at a few kV, this goes well into the GV/cm ranges. Larger and more powerful devices are a lot less sensitive since they have thicker oxide layers and larger areas for the currents to flow through once discharge does take place.
Fabs are another place where ESD can be a very significant risk. The air is so clean and pure, and exists almost only of non-polar molecules which have a lot harder time dissipating even the smallest amount of charge. The mere action of putting on bondwires can destroy IC's.
The most sensitive components are things like powerfull processors and FPGA's which end up using a very small nodes. Really sensitive components often have ESD protection internal to them.
Analog components are often a lot stronger anyways. RF stuff is an exception to this, and often can't be protected either (because the protection circuitry would just ruin the RF performance), which is why, as mentioned here, these are most prone to being damaged.
Oh, just a little afterthought: The reason most power components (like say discretes and 74 logic) don't seem to break is because they seldom fully fail: they just get damaged reducing performance (most often the leakagecurrent into the source because a "damaged" path has formed through the source oxide) and/or reliability. You might just not realize because your prototype has to work only once or you are using over-rated components anyways. You could for instance have ruined the Rds(on) causing higher temperatures, making the component die once the product is actually pushed to it's limits.
Hope I didn't mess up to bad...
Parts with a * have been added after I taken some time to read and think about my post.
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