JFET front-end amplifier a la AoE3

[guymo]

I'm slowly putting together a design for a preamp to have a look at the ripple and noise from a PSU I've built. I asked about this in the projects forum and got some very useful replies which ended up with me studying again things I thought I knew, so here I am back in the Beginners forum where I belong, with many questions.

The design I am heading towards is a pair of JFETs as a front end to an op amp. There's a bit on this in Art of Electronics 3 and what I have right now looks a lot like their design. The bare bones of it are shown in the attached.

It seems very simple and "straight from the book" but I am worried that there may be some pitfalls.

Goals are: AC coupling with cutoff in the single Hz or lower; gain of 100; bandwidth to at least 20MHz; "not too noisy" -- my scope's input noise is about 1mV pp so if the noise at the output of this is around that level I'm happy; +/-9V power from batteries.

The circuit works as intended in LTSpice but I am concerned about practicalities.

JFET matching/input offset: The 2SK3557 datasheet specifies Vgs(off) between -0.3 and -1.5V. Clearly I need to match the devices and also add a trimmer or something to get rid of offset voltage. The gain of the JFET stage should be about 10, with drain currents at around 2mA, so I think a 200Ohm trimmer connecting the drains to VCC should allow 400mV of trim there, which would cope with 40mV of mismatch at the gates. Sorting through 30 or so devices should find a pair which are at least that close. Does this thinking seem reasonable? Is there a better way to achieve the trimming?

Is it sufficient to match the JFETs for Vgs(off) and then trim, or do I also need to measure Idss, or the Vgs at the operating current? Matching for all parameters seems unlikely to be successful but perhaps I am wrong about that.

Cascode? Some circuits along these lines use a BJT cascode to clamp the drain voltage of the JFETs. In simulation this doesn't seem to make much difference to the performance -- the op-amp is keeping the drain voltages pretty steady anyway. Is there any need for a cascode?

Tail current sink What's a good design for the current sink on the tail of the pair? The one shown works fine in simulation, but actually so does a simple resistor to the negative rail. Should I be using a reference and if so are there problems associated? First thought would be something like a TL431 to create an accurate voltage drop.

Anything else? I should probably get on and build something before too long but want to be reasonably confident it might work first. If anything looks troublesome I'd love to know about it. Thanks in advance!

[Yansi]

I would run it at 1 mA Id  (2 mA tail current), becasue this seems to be the current the JFET (2SK3557) was characterized for the noise figure of 1 dB.   So I would try to replicate that.  But I stay being corrected on how to decide on the bias current.

I am not sure how did you get to those 1k loading resistors, but  make sure you will still be within the input common mode range of the opamp.  Just 1 mA drain bias will get your opamp inputs just 1V below the V+ rail, that may not fall within the common mode range of the opamp. (Is the LT part number really the one you will use?)

Add emitter resistor for the current mirror down there, to mitigate unnecessary drift.  Something like 100 ohm may do? Or use something like BCV61 anyway.

[Kleinstein]

The are two way to trim the ofset: one is at the source and one is at the drain. The source side essentially only effects the offset. Adjusting the drain resistors and thus the current ration also changes the temperature dirft. With a gain of 100 the offset is no yet that critical. With some 3 V working range for the output, one could tolerate some 20 mV of offset for the input. It would be good anyway to have a 2nd AC coupling behind the initial gain stage. The resistor to ground contributes to the noise in the transition region. So ideally the input AC coupling would be down to a frequency lower than finally wanted and the actual low frequency limit is set in a later stage, after the amplification.

20 MHz BW is pretty fast - the cascode may help there to get more speed.

The easier way my be the JFET just as a source follower open loop and than a separate fast amplifier only behind that. With the right current (some adjustment) the JFET source follower can be pretty low drift. It may be slightly more noise, but not much.

[Marco]

Input impedance/noise is going to be less than ideal at low frequencies, that's why Jim Williams used very large tantalum capacitors for his version.

The alternative is a non differential DC coupled JFET amplifier with a supercapacitor stack on the source.

[guymo]

I would run it at 1 mA Id  (2 mA tail current), becasue this seems to be the current the JFET (2SK3557) was characterized for the noise figure of 1 dB.   So I would try to replicate that.  But I stay being corrected on how to decide on the bias current.

I am not sure how did you get to those 1k loading resistors, but  make sure you will still be within the input common mode range of the opamp.  Just 1 mA drain bias will get your opamp inputs just 1V below the V+ rail, that may not fall within the common mode range of the opamp. (Is the LT part number really the one you will use?)

I do plan to use the LT1819 for the very scientific reason that I have some here... Looks quite good for the job anyway. The input common mode goes to 1.5V from the rail, at worst -- at this supply voltage the limit should be closer to 0.5V. The load resistors and bias current were chosen by a bit of experimentation in Spice. Higher load resistors led to peaking that required more compensation than I wanted, which limited the bandwidth a bit. A compromise of 1.5mA bias current and 1.5k load resistors seems to work just fine though.

The are two way to trim the ofset: one is at the source and one is at the drain. The source side essentially only effects the offset. Adjusting the drain resistors and thus the current ration also changes the temperature dirft. With a gain of 100 the offset is no yet that critical. With some 3 V working range for the output, one could tolerate some 20 mV of offset for the input. It would be good anyway to have a 2nd AC coupling behind the initial gain stage. The resistor to ground contributes to the noise in the transition region. So ideally the input AC coupling would be down to a frequency lower than finally wanted and the actual low frequency limit is set in a later stage, after the amplification.

I can't see a good way to have a highpass stage after the JFET stage, without just getting into the same issues that motivated the JFET front end in the first place. In order to highpass with a cutoff of a few Hz, I either need a very large capacitor (> 1000uF) or a very large resistor. Getting a cap like that is very expensive it seems. And to use a large resistor requires a high input impedance for the next stage, so we'd need JFETs again... unless I am missing something.

20 MHz BW is pretty fast - the cascode may help there to get more speed.

In my simulations the cascode actually reduces the bandwidth a bit. Does that mean the simulation is misleading and/or has been put together by an idiot?

The easier way my be the JFET just as a source follower open loop and than a separate fast amplifier only behind that. With the right current (some adjustment) the JFET source follower can be pretty low drift. It may be slightly more noise, but not much.

I considered that kind of design too. The issue there is getting the gain and bandwidth I'm looking for from the next stages. Cascading a couple of x10 gain stages worked ok, but was a lot noisier in the simulations: having gain at the JFET stage helps to swamp out noise in later stages I suppose.

So is the drift something to worry about? It would manifest as offset drift I guess? The Jim Williams design uses a servo to cancel the offset actively, which looks pretty interesting to try out but I was hoping to get away without it in a first attempt.

Input impedance/noise is going to be less than ideal at low frequencies, that's why Jim Williams used very large tantalum capacitors for his version.

The alternative is a non differential DC coupled JFET amplifier with a supercapacitor stack on the source.

As above, I am a bit scared of using a fancy large value cap. Jim Williams's AN-124 design, among others, has been a great read while I've been thinking about this of course. In the simulations the move from e.g. 100n/1Meg to 100u/1k makes a big difference to noise in the 0.1 - 10Hz band, but overall up to 20MHz, not much. Total output noise in that band comes to around 500uV RMS according to Spice. That is probably only just visible on my scope. This would be no good for Jim Williams's application to measure LDO noise in the sub-microvolt range of course. Is there something else lurking here for me to worry about?

Thanks to everyone for some interesting and useful replies.

[Kleinstein]

For a cross over frequency in the 1 Hz range, the capacitor does not have to be that large. Some 1 µF are readily available as a film cap with not to large a form factor and with a 1 M resistor this is well below the range were the SK3557 is really good for low noise. With a high impedance input 1 Hz and even below 0.1 Hz cross over is not so difficult.
The high pass filter with such a large resistor will add noise in the transition region. After amplification the filter noise is no longer an issue. It depends on the applicatgion if more low frequency noise is an issue.

One will need larger caps if the amplifier has higher current noise or bias - e.g. for an AZ OP or with a BJT based amplifier. The lower the frequency the larger the cap. With I/f current noise the frequency can make a boig different and 1 Hz is much easier than 0.1 Hz.

In the pass band the noise from the resistor to ground is not a proble. The noise test should be done with a shorted input, not an open input.

Temperature drift can be a slighte issue, as it makes temperature fluctuations look like 1/f noise. With a careful thermal degin it is less important, especially if there is a 2nd AC coupling stage forther down the chain.

[David Hess]

JFET matching/input offset: The 2SK3557 datasheet specifies Vgs(off) between -0.3 and -1.5V. Clearly I need to match the devices and also add a trimmer or something to get rid of offset voltage. The gain of the JFET stage should be about 10, with drain currents at around 2mA, so I think a 200Ohm trimmer connecting the drains to VCC should allow 400mV of trim there, which would cope with 40mV of mismatch at the gates. Sorting through 30 or so devices should find a pair which are at least that close. Does this thinking seem reasonable? Is there a better way to achieve the trimming?

Trimming can be done automatically with a parallel low frequency low input bias current operational amplifier measuring the difference in the gate inputs and trimming one of the JFETs.

Is it sufficient to match the JFETs for Vgs(off) and then trim, or do I also need to measure Idss, or the Vgs at the operating current? Matching for all parameters seems unlikely to be successful but perhaps I am wrong about that.

Matching can be done by Vgs(off) or Idss.  There is a correlation between them.

Cascode? Some circuits along these lines use a BJT cascode to clamp the drain voltage of the JFETs. In simulation this doesn't seem to make much difference to the performance -- the op-amp is keeping the drain voltages pretty steady anyway. Is there any need for a cascode?

The cascode reduces the Miller effect in the JFETs for better bandwidth and also allows bootstrapping for a wider input voltage range.  I doubt it is needed here.

Tail current sink What's a good design for the current sink on the tail of the pair? The one shown works fine in simulation, but actually so does a simple resistor to the negative rail. Should I be using a reference and if so are there problems associated? First thought would be something like a TL431 to create an accurate voltage drop.

It does not need to be complicated.  A simple bipolar transistor current sink should be sufficient.  An old design would likely use just a resistor to a high voltage supply like -50 volts.

Anything else? I should probably get on and build something before too long but want to be reasonably confident it might work first. If anything looks troublesome I'd love to know about it. Thanks in advance!

I think you are on the right track.  An alternative design is DC coupled and uses a low noise reference for the other input so it acts as a comparator, but this requires an input voltage range which includes the voltage you want to measure which can be complicated to implement.

[guymo]

Trimming can be done automatically with a parallel low frequency low input bias current operational amplifier measuring the difference in the gate inputs and trimming one of the JFETs.

Would you say this is superior to trimming by hand? I suppose a servo approach would cancel any drift issues.

I think you are on the right track.

Thanks -- together with the other replies and no dire warnings, this gives me some confidence. I think I will start laying out a PCB and see how I get on.

[Marco]

I think you are on the right track.  An alternative design is DC coupled and uses a low noise reference for the other input so it acts as a comparator, but this requires an input voltage range which includes the voltage you want to measure which can be complicated to implement.

A stack of super capacitors in the feedback loop works too (dunno why I thought it needed a single ended amplifier, it obviously doesn't). It's a trivial change to his circuit, just disconnect the lower resistor from the feedback divider from ground and put a stack of supercapacitors (with balancing resistors) in between. Done. It will short circuit the opamp for a bit and take a while to settle though, might want to use something which can feed a fair bit of current.

As long as you keep the amplification of the stage reasonable, the supercapacitor leakage current won't drive the stage into saturation (and any DC offset will obviously never even arrive at the next stage).

[David Hess]

Trimming can be done automatically with a parallel low frequency low input bias current operational amplifier measuring the difference in the gate inputs and trimming one of the JFETs.

Would you say this is superior to trimming by hand? I suppose a servo approach would cancel any drift issues.

As usual, it depends on the application.  A separate offset control loop works for this type of measurement but would not be suitable if the input was subject to overload and fast recovery time was required.

In this case there is no reason not to use an offset control loop; I do not think you will get as good a result with manual trimming unless you make a heroic effort to control offset voltage drift and flicker noise.  The operational amplifier should have low input bias current, good precision, and low flicker noise.  Chopper stabilized amplifiers can be acceptable, but so are precision low noise FET and superbeta parts like the LT1008/LT1012/LT1097.

A stack of super capacitors in the feedback loop works too (dunno why I thought it needed a single ended amplifier, it obviously doesn't). It's a trivial change to his circuit, just disconnect the lower resistor from the feedback divider from ground and put a stack of supercapacitors (with balancing resistors) in between. Done. It will short circuit the opamp for a bit and take a while to settle though, might want to use something which can feed a fair bit of current.

As long as you keep the amplification of the stage reasonable, the supercapacitor leakage current won't drive the stage into saturation (and any DC offset will obviously never even arrive at the next stage).

The figure of merit would be leakage for a given capacitance, with maybe some size restrictions.  Supercapacitors of any type completely fail in this application because of massive leakage and dielectric absorption.  Jim Williams used a wet tantalum capacitor with good results.  Low leakage aluminum electrolytics can work but settling time is hours to days, and temperatures need to be stable.

The above is why low input bias current is important.  The lower the input bias current, the less capacitance is required for a given low frequency cutoff.

[Marco]

Supercapacitors of any type completely fail in this application because of massive leakage and dielectric absorption.

The leakage doesn't matter on the feedback side of the differential pair as long as it doesn't drive the amplifier into saturation and dielectric absorption doesn't matter for an AC amplifier.

The figures of merit for the capacitor for an AC amplifier which does filtering on the feedback side are different from just doing it on the input.

[Kleinstein]

There is not that much difference between the capacitor in the feedback path or at the input. Dielectric absorbtion can still lead to some long lasting drift and the leakage current leads to some offset. In the FB path one can however chose a different impedance level, like the very large capacitance and relatively low resistance way with a super cap.
The DC offset from leakage would not be that bad and would not saturate the amplifier. The slow settling drift from DA can be a bit anoying, but an additional AC coupling after the amplifier should remove most of it.

There is another potential problem with the supercaps: there will very likely be some temperature sensitivity. So temperature variations can show up - not sure how much, but it can be pretty bad.
The filter cap gets increasingly more tricky the lower the frequency. 0.1 Hz lower frequency limit is still possible with a classic film cap of some 10 µF with a low bias (and low current noise) amplifier.  A relatively large resistor is not directly contributing to the noise, except for the transition region. The problem is more with the amplifiers noise, as current noise from a BJT based amplifier or AZ OP and the 1/f noise part of JFETs.   

[guymo]

I'm very grateful for all this discussion. I have some questions which I fear may be a bit on the dumb side -- please forgive!

I don't quite grasp the topology proposed by Marco. As I read it, it would be something like the attached, where the amplifier symbol refers to the whole composite amplifier (jfet input stage and op amp, open loop). But this seems to have a DC gain of 1, so I'd still need to highpass the input, which takes me back to where I started. So I think I must have misunderstood what was proposed. Can someone set me straight please?

As for the offset control loop, I can see two different ways to approach it. One is to sample the gate voltages with an integrator and adjust the drain current of one of the JFETs to make them equal. The other is to sample the output voltage and adjust the input gate voltage via the 1Meg resistor to hold the output average at zero. The second approach seems easier to implement and looks ok in simulation. Are there any gotchas there? I found it introduced some peaking at low frequency, I guess because of a pole in the response caused by the offset loop, which I compensated with a passive lowpass before the integrator. Does this look reasonable?

Thanks again.

[Marco]

I don't quite grasp the topology proposed by Marco. As I read it, it would be something like the attached, where the amplifier symbol refers to the whole composite amplifier (jfet input stage and op amp, open loop). But this seems to have a DC gain of 1

A DC gain of 1 is not a problem for measuring power supplies, it's easy to make an amplifier for which that is in the dynamic range. Lets say you get your 0.1-10 Hz 100x amplified signal on top of the DC amplified by 1x, it's easy to make a high pass filter after that stage, the requirements for that filter are much relaxed from one directly on the input.

As for the offset control loop, I can see two different ways to approach it. One is to sample the gate voltages with an integrator and adjust the drain current of one of the JFETs to make them equal. The other is to sample the output voltage and adjust the input gate voltage via the 1Meg resistor to hold the output average at zero. The second approach seems easier to implement and looks ok in simulation. Are there any gotchas there? I found it introduced some peaking at low frequency, I guess because of a pole in the response caused by the offset loop, which I compensated with a passive lowpass before the integrator. Does this look reasonable?

Another advantage of having the high pass filter in the feedback ... the offset stops mattering, it doesn't get amplified.

PS. here's an example of scientists using the approach in practice, though they didn't use a differential pair approach (I think their way of bootstrapping the drain voltage is a bit overcomplicated, also you don't strictly need it, can improve linearity and bandwidth a bit).

[guymo]

I'd like to update this thread with my thanks and appreciation for the guidance and encouragement you all offered above. I've finally put together an amplifier based on the design in the first post above, and it seems to work very well for my purposes. I also have a PCB to build up with a version that servos the offset; still awaiting a couple of parts for that. But I am very hopeful for it, and very happy with the device I've already got. I couldn't have imagined putting something like this together a few months ago and have learned a great deal from working through it. So thanks!

[Kleinstein]

The simulation schematics still has a few points to improve: The current mirror works well in the simulation and on a chip, but with discrete parts there should be emitter resistors to improve in the thermal stability. The DC loop would compensate much of the effect, but still not ideal.

As shown the DC loop would determine the very low frequency noise, from about the low frequency cross over. One could reduce the noise of the OP in the cross over region with a divider at it's output - one usually does no need the full control range of the OP. As a side effect this would lower the cross over.

On the cross over region of the input RC combination the large resistor will contribute to the noise. Ideally one would have the input limit a bit lower than finally needed and do the final low frequency cut off after the amplifier.

[guymo]

The simulation schematics still has a few points to improve: The current mirror works well in the simulation and on a chip, but with discrete parts there should be emitter resistors to improve in the thermal stability. The DC loop would compensate much of the effect, but still not ideal.

I did change the schematic for the current mirror to the attached; happy to hear of further improvements of course.

As shown the DC loop would determine the very low frequency noise, from about the low frequency cross over. One could reduce the noise of the OP in the cross over region with a divider at it's output - one usually does no need the full control range of the OP. As a side effect this would lower the cross over.

I like this idea. Thank you. On the version I have built up, the input offset without trimming was pretty small thanks to matching the JFETs by hand, so I think the required output range of the servo is quite narrow. To give it plenty of headroom I guess a 1/10 divider might make sense? What sort of resistor values would you use? The comment about lowering the crossover frequency makes me think you might use quite large ones -- anything small would have an insignificant effect on the crossover, wouldn't it?

On the cross over region of the input RC combination the large resistor will contribute to the noise. Ideally one would have the input limit a bit lower than finally needed and do the final low frequency cut off after the amplifier.

I confess I have not thought much about the low end of the frequency range. My application was focussed on seeing what remained of switching noise from a buck converter after some filtering and LDO stage. I had just wanted to make the best power supply I could... but now of course I am falling into the trap of making the best measurement system I can... So I will implement this idea in the final version. Thanks again!

[Kleinstein]

The divider after the servo can be quite high in impedance. There is a 1 M (possibly 10 M in some implementations) resistor in series anyway. A 1/10 divider (like 1 M and 100 K) is reasonable. The time constant for the DC servo would in this case in crease 10 fold. The 100 K would add the the 1 M for the input coupling, so a minor (and not bad) effect only.

The OP for the DC servo does not have to be a very low noise or very low offset type. It would be relative to the amplifier output.
With well matched FETs one could also get away without the DC servo, though it usually does not hurt and can help in case of high gain.

[Terry Bites]

You don't need a cascode unless you are looking for very high bandwidth (MHz).
The servo circuit simply removes the offset by adding an small voltage to input ground.
It measures the output DC voltage, integrates (averages) it over a fairly long period before adding it to the input ground.
It will stop doing this and stabilise when the input of your amplifer is equal to the offset voltage of the integrators opamp.
It also limits the low frequency response -lower than you input CR so you wont notice the effect.
Current source stabilty is not crucial- it affects offset and again is compensated by the integrator. https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwi-iKuk4oryAhWOUMAKHVZSCdoQFjABegQIChAD&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fsboa242&usg=AOvVaw0FIwlsgu2oaj8_B8n6vF7x
Simulations of this current source are misleading- the assume that transitors with the same part number have identical specs- they dont.
Though this curent source does not need to be accurate becasue its an AC amplifier.
If you wanted to get fancy about is you would want matched jfets an a matched pair of tranistors. They cost a lot more than the individual parts.
BTW, you an make the current source with a single jfet

[guymo]

I still need to put together a polished version of this amplifier but I am posting in excitement because today I finally got hold of a function generator and was able to test the bandwidth, which ended up being 51MHz. There is a bit of peaking around 40MHz and I guess killing that might reduce the -3dB frequency a bit but for now I am unreasonably pleased with this. Thank you again to everyone who helped me out!