I'm slowly putting together a design for a preamp to have a look at the ripple and noise from a PSU I've built. I
asked about this in the projects forum and got some very useful replies which ended up with me studying again things I thought I knew, so here I am back in the Beginners forum where I belong, with many questions.
The design I am heading towards is a pair of JFETs as a front end to an op amp. There's a bit on this in Art of Electronics 3 and what I have right now looks a lot like their design. The bare bones of it are shown in the attached.
It seems very simple and "straight from the book" but I am worried that there may be some pitfalls.
Goals are: AC coupling with cutoff in the single Hz or lower; gain of 100; bandwidth to at least 20MHz; "not too noisy" -- my scope's input noise is about 1mV pp so if the noise at the output of this is around that level I'm happy; +/-9V power from batteries.
The circuit works as intended in LTSpice but I am concerned about practicalities.
JFET matching/input offset: The 2SK3557 datasheet specifies Vgs(off) between -0.3 and -1.5V. Clearly I need to match the devices and also add a trimmer or something to get rid of offset voltage. The gain of the JFET stage should be about 10, with drain currents at around 2mA, so I think a 200Ohm trimmer connecting the drains to VCC should allow 400mV of trim there, which would cope with 40mV of mismatch at the gates. Sorting through 30 or so devices should find a pair which are at least that close. Does this thinking seem reasonable? Is there a better way to achieve the trimming?
Is it sufficient to match the JFETs for Vgs(off) and then trim, or do I also need to measure Idss, or the Vgs at the operating current? Matching for all parameters seems unlikely to be successful but perhaps I am wrong about that.
Cascode? Some circuits along these lines use a BJT cascode to clamp the drain voltage of the JFETs. In simulation this doesn't seem to make much difference to the performance -- the op-amp is keeping the drain voltages pretty steady anyway. Is there any need for a cascode?
Tail current sink What's a good design for the current sink on the tail of the pair? The one shown works fine in simulation, but actually so does a simple resistor to the negative rail. Should I be using a reference and if so are there problems associated? First thought would be something like a TL431 to create an accurate voltage drop.
Anything else? I should probably get on and build something before too long but want to be reasonably confident it might work first. If anything looks troublesome I'd love to know about it. Thanks in advance!