JFET frontend amplifier stability

[FaTiWo]

Inspired by The Arts of Electronics 3 and this post (https://www.eevblog.com/forum/beginners/jfet-front-end-amplifier-a-la-aoe3/msg3579870/#msg3579870) I started to play around in LTSpice with an JFET frontend amplifier.
I am not very familiar with analogue electronics, but such an approach seems to me to be suitable for both small (several 10 ohms) and large (several 10 kohms) signal source impedances due to the relatively low voltage noise as well as the low current noise of the JFETs (and of course also the large input impedance).
My intentions/goals for such an amplifier are:
- low noise (hence jfet frontend)
- as linear as possible (hence the feedback with the OpAmp)
- stable for resistive and iductive signal sources
- bandwidth of several 100 kHz (low input capacitance)

While running simulations in LTSpice, I found that the circuit seems stable, but with the wrong impedance at the input, it is not. This is especially true for inductive sources such as a measuring coil with a few hundred uH. If there is a nearly resistive source everything works fine. I did not expect this, as I have only worked with instrumentation amplifiers when amplifying a signal from a coil, and they always worked stably. So my first question would be, if there is any possibilty to make this circuit more stable?

While investigating this question, I randomly experimented with an RC element at the input, which can make the circuit much more stable. But that looks scary to me and I do not really trust it, especially with regard to a practical implementation. I think that the instability is due to the real part of the input impedance of the amplifier circuit, which no longer becomes negative with the RC element. I explain this as follows:
If the input resistance becomes negative in a certain frequency range and the resonance frequency of the LC element (consisting of the input inductance and the parasitic capacitance) falls into this range, the resonance is not damped as it would be with a positive resistance, but instead amplified uncontrollably. Is this right? Does such a problem come from the amplifier topology or is it a general problem of amplifiers?
Furthermore, it irritates me that according to my interpretation of the phase and amplitude of the feedback amplifier, the circuit with RC element should still be unstable. However, the transient analysis in LTSpice works perfectly. Any ideas why?
Another solution in relation to the negative real part of the input impedance would be to put a resistor in front of the gate, but that is an bad idea for low noise purposes.

The schematic and some graphs illustrating the problems discussed above can be found in the attached.
Thanks in advance!

[TimFox]

When designing high-frequency feedback circuits for use with tuned circuits (ballpark 20 MHz), I found it useful to do .AC analysis (linearized) on the Spice model without source impedance, and "measure" the complex input admittance with a dummy voltage source connected to the input.  Often, one could find a region of frequencies where the real part (conductance) was negative, which could cause oscillation if the source conductance at that frequency were not sufficiently positive.
With an inductive source, watch out for the "Colpitts oscillator" (q.v.) circuit formed by the JFET input (gate-source) capacitance and the bypass capacitor across the source bias resistor.

[FaTiWo]

All right, the AC analysis shows me a frequency range with negative conductance. Does this mean that the amplifier can only be used for sources with sufficient positive conductance? How do professionals solve something like this when they develop a product? Is it possible at all?

Does the problem occur especially in high-frequency feedback circuits or does the reduction of the bandwidth already provide a fix?

And did I understand correctly that there is a direct correlation between the "Colpits oscillator" and the negative conductance?

[Kleinstein]

R15,R16 and C3 in the circuit shown are parts to deal with the input impedance. With suiteable values there one can avoid oscillation and make the input impedance well behaved again.

Limiting the BW of the amplifier can help a little, when done directly at the JFETs. Just the normal capacitor (c2) parallel to the feedback part usually does not help.  It sometimes helps to use JFETs / transistors that are not as fast. The LSK389 don't look very fast, more like made for the audio range and not RF. So things may get worse with faster parts.

[iMo]

In LTSpice you can do "stability analysis".

https://www.analog.com/en/technical-articles/ltspice-extracting-switch-mode-power-supply-loop-gain-in-simulation-and-why-you-usually-don-t-need.html

Below an example..

[TimFox]

And did I understand correctly that there is a direct correlation between the "Colpits oscillator" and the negative conductance?

There may not be a direct correlation, but the usual biasing circuit with a bypassed source resistor is the same topology as a Colpitts oscillator, when you include the gate-source capacitance of the JFET.
If you can directly ground the JFET source terminal, that's great.  Otherwise, you must look at the actual values of the two capacitors.

[Gerhard_dk4xp]

You have hit a pet peeve of mine, since several years.
That is the same mechanism as a capacitively loaded follower
and it is really hard to correct. The usual cure is to insert a
positive resistance into the input, but it may need to be so
much that the amplifier is no longer low noise because of
the thermal effect of the resistor.
Usually it goes also away when you cut the feedback into the
source.
This here is the amplifier from AOE3, some values have been
changed to search for sensitivities. I have countless other
examples, some of which brought me hostility from their authors.

The function re() in LTspice returns the real part, input AC voltage
divided by input current is input resistance.
This is the yellow trace in the plot.
I also have measurements with the network analyzer.

Must go now to mow the lawn before it starts raining.
Cheers, Gerhard

[magic]

I have simulated a similar circuit with a differential input stage and an opamp second stage with Miller compensation. Closed loop BW is ~2MHz.
In my case it appears that gate current is strongly correlated with gate-drain voltage, consistently leading it by 90° as is expected from a capacitor. This makes sense I guess, because the input stage is designed to have high gain and therefore drain voltage swing exceeds gate-source voltage swing significantly.
The input resistance anomaly occurs when gate current phase is near 180°, in the ±(90°~270°) regions. This corresponds to gate-drain voltage phase being -180° to -360°. It seems to begin exactly at the closed-loop -3dB point.

[FaTiWo]

Hi again,

sorry for my late reply, I was busy the last few weeks. I will go through your answers chronologically and ask anything what comes up to my mind. For me this is a very interesting topic.

R15,R16 and C3 in the circuit shown are parts to deal with the input impedance. With suiteable values there one can avoid oscillation and make the input impedance well behaved again.

Limiting the BW of the amplifier can help a little, when done directly at the JFETs. Just the normal capacitor (c2) parallel to the feedback part usually does not help.  It sometimes helps to use JFETs / transistors that are not as fast. The LSK389 don't look very fast, more like made for the audio range and not RF. So things may get worse with faster parts.

LTSpice confirms to me that with carefully chosen values of R16 and C3 it is possible to make the real part of the input impedance positive, mainly at the expense of additional input capacity. But for me it is quiet unclear why R16 and C3 help to solve the problem. Are there any explanations? Can one see this on an Smith chart or what do I have to pay attention to? Of course, as also mentioned by Gerhard, the gate stopper resistor R15 always helps (the easiest way to improve the input resistance) with the disadvantage of much higher noise.
How do I limit the BW of the amplifier directly at the JFETs?

There may not be a direct correlation, but the usual biasing circuit with a bypassed source resistor is the same topology as a "Colpitts oscillator", when you include the gate-source capacitance of the JFET.
If you can directly ground the JFET source terminal, that's great.  Otherwise, you must look at the actual values of the two capacitors.

Why does grounding the JFET source connection help? If I understand you correctly, I would assume that this breaks up the "Colpitts oscillator" structure, right?

You have hit a pet peeve of mine, since several years.
That is the same mechanism as a capacitively loaded follower
and it is really hard to correct. The usual cure is to insert a
positive resistance into the input, but it may need to be so
much that the amplifier is no longer low noise because of
the thermal effect of the resistor.
Usually it goes also away when you cut the feedback into the
source.
This here is the amplifier from AOE3, some values have been
changed to search for sensitivities. I have countless other
examples, some of which brought me hostility from their authors.

The function re() in LTspice returns the real part, input AC voltage
divided by input current is input resistance.
This is the yellow trace in the plot.
I also have measurements with the network analyzer.

Must go now to mow the lawn before it starts raining.
Cheers, Gerhard

It irritates me that this is apparently not perceived as a problem, but for me LTSpice is clear in transient analysis - it oscillates with an inductive source with some uH.
From your answer, I conclude that it is best to choose an amplifier topology where the feedback goes back to the gate of the JFET. Or what do you mean by "cut the feedback into the source"?
Another idea from me would be to shift the negativ real part of the input impedance to higher frequencies (above a few 100 MHz) and then uses ferrite beads in series to the gate of the JFETs to add additionally impedances. But it is completely unclear to me whether this is even possible to shift the negative resistance in the higer frequency range...

[magic]

The admittance of two circuits in parallel is the sum of the individual admittances.
If one has negative admittance and the other positive, the sum can be made positive or even zero in theory.

Don't plot impedance, plot what input currents flow into the amplifier and the RC networks in front of it. If they are out of phase, they will partly cancel. And figure out whether the offending current flows into the gate-source capacitance or gate-drain; in my toy simulation GD appears to be the deciding factor.

[TimFox]

my reply:
Quote from: TimFox on October 01, 2021, 09:05:39 am

    There may not be a direct correlation, but the usual biasing circuit with a bypassed source resistor is the same topology as a "Colpitts oscillator", when you include the gate-source capacitance of the JFET.
    If you can directly ground the JFET source terminal, that's great.  Otherwise, you must look at the actual values of the two capacitors.

Why does grounding the JFET source connection help? If I understand you correctly, I would assume that this breaks up the "Colpitts oscillator" structure, right?

This is just a hint from my experience designing low-noise JFET amplifiers that were driven from a resonant circuit.
I found the safest connection to be grounding the JFET source directly to the ground plane, with the resonant circuit connected between the gate and ground, with a DC block in series with the gate to allow a DC bias network.  I usually had a cascode connection to minimize the Miller effect of the drain-gate capacitance.
The analytic process I used with more complicated feedback amplifiers used a linearized Spice calculation and "measuring" the complex admittance at the input to look for possible out-of-band or in-band regions of negative conductance.

[Gerhard_dk4xp]

> It irritates me that this is apparently not perceived as a problem, but for me LTSpice
> is clear in transient analysis - it oscillates with an inductive source with some uH.
> From your answer, I conclude that it is best to choose an amplifier topology where
> the feedback goes back to the gate of the JFET.
> Or what do you mean by "cut the feedback into the source"?

In reply#6, remove C5/R9, the hot side of the feedback divider.
No more feedback. no more negative Rin. Replacing the op amp with a vcvs removes the
problem also, but they a hard to get in hardware. I found an ultrawide BW op amp from
TI that is fast enough, but it has very bad 1/f noise so that the input stage has no influence
on the noise; it's real real reason to exist. 

You could slow down the FET stage until the op amp in the loop is fast enough by
Millering the FETS to slow motion. But then the bandwidth would be ridiculous,
the cascode would make no more sense and input C would be huge.

>Another idea from me would be to shift the negativ real part of the input impedance
> to higher frequencies (above a few 100 MHz) and then uses ferrite beads in series to
> the gate of the JFETs to add additionally impedances. But it is completely unclear
> to me whether this is even possible to shift the negative resistance in the higher frequency range...

Complicating things at higher frequencies is not a good idea. In my array of 16 CPH3910
there were enough resonant structures and coupling to make it oscillate at 650 MHz via
a strictly local mechanism, without involving the op amp and feedback path.
Funny enough, every FET had different RF voltages, measured with a 0.6pF 2.5 GHz probe/scope.
Even though they were connected on the board with traces of just a few mm.

I was then fed up enough and gave each FET it's own gate bead and a drain capacitor to ground.
These Cs had to be quite substantial because the drain load is the emitter of the folded cascode,
that equals just a few Ohms. I used as much as possible without hurting the amplifier bandwidth
of a few MHz. But I did not accept negative input impedance in a measuring amplifier.
Early tube-based TEK scopes had that problem too.

The problem is not only in simulation, it exists in real life. The Smith plot is from a similar
amplifier with Interfet IF3602. The trajectory leaves the unit circle (given by 0+j0 and inf+j0)
That means that more energy comes back from the input port than is sent into it. --> unstable
with the wrong input termination. At the cursor positions, the S11 is decoded to Z for this frequency.

Don't spend €60+  a pop for IF3602 (Mouser). They are not worth it. Even the revised data sheet is
optimistic.

I also removed the feedback around the FETs for good. Gain was stable enough. I also had a version
that kept the FETs at 40°C, that was not necessary.

[FaTiWo]

Thanks for your answers. I will try out some thing you suggested to me - of course in simulation, anything else would probably be far too error-prone.

In the meantime I have done some simulation similar to that Gerhard posted in replay #6. Out of interest, I have broken up the feedback loop by removing the equivalent of C5/R9. Nevertheless I observ the negativ real part of the input impedance as soon as I connect the ADA4898 OpAmp model in an transimpedance amplifier configuration to the JFET drain. May that could be because the OpAmp is already to slow for such kind of feedback? I attached the corresponding LTSpice schmatic and diagrams.

You could slow down the FET stage until the op amp in the loop is fast enough by
Millering the FETS to slow motion. But then the bandwidth would be ridiculous,
the cascode would make no more sense and input C would be huge.

........

I was then fed up enough and gave each FET it's own gate bead and a drain capacitor to ground.
These Cs had to be quite substantial because the drain load is the emitter of the folded cascode,
that equals just a few Ohms. I used as much as possible without hurting the amplifier bandwidth
of a few MHz. But I did not accept negative input impedance in a measuring amplifier.
Early tube-based TEK scopes had that problem too.

First you said that one has to make the Miller capacity quite huge to slow down the FET and you pointed out that this only makes limited sense, especially when one uses a cascode. But then when you go one with the description of your array of 16 CPH3910 you mentioned that you used aditionally capacity from the FETs drain to ground,  to get rid of the negativ real part input impedance problem. My understanding is that this corresponds to an increase in Miller capacity. So I conclude that increasing the miller capacity is the only solution even if it is unpleasant. Do I get this correctly?

[Gerhard_dk4xp]

NoNoNo, there are two oscillation mechanisms.

One is the oscillation at 650 MHz, which is due to just the FETs and their gate/drain
wiring and resonances. This one is helped by the gate beads and UHF decoupling
of the drains with caps to ground. You cannot see this in spice because you cannot
model the resonating wires and their coupling in Spice, at least not easily.
There may be different methods of killing the gain at 650 MHz, like slight Miller that does
not kill the gain at 5 MHz or small beads also in the drain.  I was unsure about the
coupling effects between the additional beads in the drain; small resistors might work
also but would have messed up my layout.

I needed 16 parallel FETs to reduce the input noise voltage, but 16 times CPH3910
results in a huge gm that can bite one easily, and this FET is fast, a completely different
animal than the 2sk170 that is no longer available from trustworthy sources.

Individual beads on the gates and individual Cs at the drains worked for me. I left it
this way because the FET amplifier had already eaten way too much time.
Maybe one could reduce the effort but I won't be the one to fathom that out.
---

The other oscillation mechanism is negative input resistance. If you look at the FET,
you note an Ohm or so to ground and you conclude that the stage must be a
common source amplifier. The drain current goes to the cascode, fine. Then comes
the op amp for more loop gain and then the feedback resistor to set the overall gain.

But now with the feedback, the source is no longer at ground. It follows the gate ac
voltage quite closely. The drain still looks into the low impedance cascode input.

For the FET, the world now looks different. It thinks it works as a follower. And
capacitively loaded followers like to oscillate and to develop negative input resistance.
That is how most VHF VCOs work and it's textbook stuff how the negative input
resistance is generated.

The seemingly capacitive loading at the source comes from the phase shift of
the feedback loop, mostly from the op amp. A VCVS makes it much easier.


-------
BTW from my spice lib file since you seem to use the 4898:

*ADA4898 Macro-model
* The version  08/10/2012 does not work. wrong noise, phase slope etc
* This one still features problematic convergence.  (gerhard)
*Rev.2.1 Apr 2017-ZZ
*Copyright 2017 by Analog Devices
I have the impression that even the new model has convergence problems
when there are 2 or more incarnations in the LTspice file.
I have no idea why.  TI  LME49860 model has less surprises.

cheers, Gerhard

[guymo]

I have broken up the feedback loop by removing the equivalent of C5/R9.

Have you? To me it looks like R5/C3 in the current schematic are the equivalent of Gerhard's C5/R9. If I understand correctly, the suggestion is to run the amplifier open-loop. I guess you can just measure the gain rather than calculating it from the feedback arrangement.

[Gerhard_dk4xp]

On microcontroller.net, there has evolved a similar thread.
I put mutuals pointers since I don't want to repeat everything.

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