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JFET mysteries
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hirada:
Hello all,

So I've thought to finally having found the holy grail for high side switching in symetrical JFETs, simply connect the source to V+ and when the Gate is high, VGs=0 and it conducts, when the gate is low, Vg<Vs, so it blocks, and therefore I went shopping and done some testing during the last days.

Of course, it was an utter failure. Now I am not sure wether I have misunderstood the interchangeability of Drain and Source mentioned in the specs or wether I just may have killed both JFETs while soldering them to the SOT23->through hole adapter. I am not the worlds most skillfull SMD solderer.

Anyway, the big disappointment was, that they completely behaved identical, no matter wether I connected Source or Drain to V+.

So no matter which way I've connected them, they always behaved, as if the reference voltage for the gate was the voltage on the terminal closer to ground and not fixed to the voltage on the source terminal, as suggested by the datasheets.
Meaning what is specified as Vgs practically has kind of become Vds and therefore defying any meaning of connecting them upside down. For me interchangeability meant, that current may flow in both directions, but not, that the reference voltage for the gate switches as well.

But maybe I have done something fundamentally wrong. Hence my cry for enlightenment.


The other mystery is, when the Gate is high (that is V+) and I am disconnecting V+ from the source (or drain, if connected instead), the gate current rose dramatically from a couple of μV to up to half a milliamp and more. In fact the gate current equalled the drain current (or source current, if connected the other way round). Enough to dim the LED and so we are not talking about the initial gate current needed to charge the gate capacitor.

What is this? Is this the mysterious "Forward Gate Current" found in the datasheets and that I have yet to find an explanation for?

And why would anybody want to do this that makes it worth being specified in the datasheet? It was a mistake on my side, that made me discover this behaviour, but why would anyone run a JFET without one terminal being connected?

Thanks for any insight

Edit: The ADG419BN in the picture is really just a placeholder for a manual switch to change the gate voltage between GND and V+.
oPossum:
What is the part number of the JFET you are using?
hirada:
Sorry. I knew I've forgotten something. Here we go:

PMBFJ109
https://www.nxp.com/docs/en/data-sheet/PMBFJ108_109_110.pdf?

PMBFJ309
https://www.nxp.com/docs/en/data-sheet/PMBFJ308_309_310.pdf?
madires:
The FET Constant-Current Source/Limiter: https://www.vishay.com/docs/70596/70596.pdf
Kleinstein:
Most of the JFETs are really that symmetric - so there is no difference between the source and drain terminals. For a N channel JFET the relevant voltage is between the gate and the more negative D/S  pin.  So for switching one may need to provide an auxiliary signal at the level to switch for the on phase.

There are a few non symmetric JFETs, usually for RF applications. Here the gate to source and gate to drain capacitance can be different and also the trans-conductance could be different when D and S are interchanges. However if used for simple slow switching  one could still interchange drain and source.

It is not normal to use a JFET with 1 terminal open. But there are uses with 2 pins directly connected. Either as a current limited (G connected to source) and as use as a low leakage diode (D and S together).
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