Jutter calculation ?

[GigaJoe]

I'm right ?
Jitter 1.5 nS
or it should be divided in 2 -- 750pS



 

[ataradov]

You are triggering on the rising edge, but measuring the falling edge. This is not a meaningful measurement for the typical clock application. You need to measure edge to edge. Then the measured value would be the period jitter.

[GigaJoe]

Okey ! Thanks !

so period ...  1nS , limit


hmm ... hard to say how much is that ...

or I measure something incorrectly, again ....

[ataradov]

This is not a lot of period jitter.  Next step is to move away multiple periods until there is a measurable value and then divide by the number of periods. But the more periods you move away, the less meaningful this number becomes from the characterization point of view. It is still good enough for basic estimation.

What is the signal source and what is the anticipated jitter?

[GigaJoe]

Im playing with DSS  FY-6900
and as many complain about jitter signal output , I'm trying to actually characterize it in numbers.

so gen source is 10Mhz OCXO now .. and I can run output up to 60M  ; that frequency on pictures  is actually 10.000 000.1

my guess I need to pick some most horrendous frequency but I don't know what is that ;  like completely uneven , random one ?

[ataradov]

Well, you need to get information from the people that complain. It is possible that it is much worse with certain types of signals and/or frequencies.

Also, is that 10 MHz reference external? Is it possible that it is bad with internal reference only?

I have no idea about that specific siggen.

But also, since you are characterizing a general purpose signal generator, your initial measured duty cycle jitter also matters. If you are using it for something that cares about duty cycle, it may not fit your needs.

[bdunham7]

When you generate a square wave or pulse with DDS signal generators at anything but a submultiple of the DDS clock, you'll get varying rise times but the AWG will typically try to minimize the jitter as measured at the zero crossing or the midpoint of the waveform if it isn't symmetrical around zero.  IOW, that really isn't jitter, at least not it the way that it is typically defined.

[adeuring]

Im playing with DSS  FY-6900
and as many complain about jitter signal output , I'm trying to actually characterize it in numbers.

so gen source is 10Mhz OCXO now .. and I can run output up to 60M  ; that frequency on pictures  is actually 10.000 000.1

my guess I need to pick some most horrendous frequency but I don't know what is that ;  like completely uneven , random one ?

I'm writing this based mostly on knowledge about the FY6600 I gathered from reading relevant threads of this forum about the FY6600. AIUI, the FY6900 has only minor modifications, so I assume that the following applies to the FY6900 too.

The FY6600 has an FPGA that is "clocked" from an external 10MHz crystal oscillator. The FPGA has an internal PLL (or has it two PLLs? – I would have to look at the schematics of the FY6600, find the FPGA type and then look into its datasheet, but I'm too lazy to do that now...) The PLL generates a 250MHz clock signal. This clock signal is used to "update" the DACs that generate the output signal.

This "DAC update frequency" is never changed and this means that the FY6600 can only generate "exact" signals with periods that are an integral multiple of 1/250e6 seconds, or 4 ns.

You tried a 10MHz signal, or a period of 100ns. so you have exactly 25 "DAC updates" for one period. Hence you won't see the jitter about which some people complained.

The "neighboring exact periods" are 24 and 26 "DAC updates" per period, or periods of 24*4ns -> 96ns and 26*4ns -> 104ns, i.e. the frequencies 10.416666...MHz and 9.651538...MHz, respectively. (Note that these frequencies cannot be exactly represented as decimal numbers, so it is impossible to set the generator output to these frequencies – or is it possible to set signal periods instead of signal frequencies with the FY6600/FY6900?)

So, if you set the output frequency for example to 10.2MHz, you will get an output signal where the period alternates between 24 and 25 "DAC updates" (96ns and 100ns) per period, so that the period, when averaged over a longer time, equals 1/10.2 µs. Similarly,  when you set the output frequency to 9.8MHz, the output signal will have periods that alternate between 100ns and 104ns,

This should be easily visible on your DSO as two lines separated by 4ns when you look at the signal one period before and after the trigger time.

When you choose frequencies that are closer to 10MHz but not exactly 10MHz, the lines on the DSO screen showing the periods 96ns or 104ns should become darker.