Latching Power Circuit

[zenekNY]

Hiii!

I am working on a device that needs a soft latching power circuit and I am very limited on a PCB space as well as trying to keep the circuitry simple.
The plan is to share a dual N channel mossfet used by a Li-Po protection IC with the soft latching circuit. but I cannot get the power to cut-off.
My attempt was to interrupt an OD (Over-Discharge) line coming from the protection IC to one of the gates on the mossfet.

Can you guys please take a peek at this circuit and tell me what am I doing wrong?

Please let me know if you need any more information or if I am not clear enough on what I am trying to do. This circuit is just to test my idea and is a part of a bigger circuit.

[JustMeHere]

Maybe you can find your answer here:
https://www.allaboutcircuits.com/textbook/semiconductors/chpt-7/silicon-controlled-rectifier-scr/

[zenekNY]

Thank you for the suggestion, the SCR sounds like a very interesting concept.
However I tend to believe that the problem lies somewhere between the OD pin of the protection IC and the gate of the MOSFET.

It looks as if the gate of the MOSFET doesn’t draw enough current (if any at all) for the PNP transistor to function properly, but when I pull the Collector of the PNP(gate of MOSFET too) down to the negative of the battery using even 5M ohm resistor it cuts the power off and the transistor is not able to pull that line back up.

[ledtester]

Since a microcontroller can be put into a sleep mode where it draws very little power (microamps or even nanoamps) I would look at simplifying the problem by always having the microcontroller powered by the battery. That way it can always control whether power is delivered to the rest of the circuit.

Then add another MOSFET in series with the other protection MOSFETs. This MOSFET is controlled by the micro and implements your soft power switch function.

[JustMeHere]

You need bleed resistors on all mosfet gates.  They will not turn off themselves unless they are pulled to ground with NPNs and pulled up with PNPs.    You should also have a small resistor between any micro pin and the gate of a mosfet.  This helps stop the capacitance of the mosfet from damaging the micro's output pins.  Even if your micro ground's its pins when it's logic low, you should have the bleed resistor.  This is because micros will high-z their pins when being programmed or booting.

[zenekNY]

The problem with keeping the entire system on, is that I have a bunch of other things running.
Unless I would be able to disable them all when the micro is “SLEEPING”
Those would be 5V boost, OLED display and accelerometer.
I thought that the easiest way would’ve been to cut the power to it all and call it the day.
Would adding a third Mosfet make sense? I know that there is a power loss and heat dissipation to be taken in consideration too, so I would like to avoid any power inefficiencies if possible since the whole thing is running on a Li-Po battery and the space is very limited.

As far as pulling the Gates on Mosfets UP/DOWN, I was under impression that the protection IC was already taking a care of that in some way as the suggested wiring diagram didn’t include any pullup/pulldown resistors.
But I attempted to pull one of the gates down using a 5M ohm resistor, which caused the power to be cut off, but wouldn’t stay latched on after I released the button.

[ledtester]

> The problem with keeping the entire system on, ...

The uC is always on, but it controls a MOSFET which delivers power to your other things. GPIO pins configured as outputs remain driven even in sleep mode.

> Would adding a third Mosfet make sense? I know that there is a power loss and heat dissipation to be taken in consideration too,

I would just try it and see how well (or not) it works - it's simple to implement.

If you don't want to add a third MOSFET, you can implement some sort of logical AND functionality for the gate of the OD MOSFET... i.e. the OD MOSFET is on if the OD signal is high AND the uC wants the power on.

[ledtester]

Just had an idea... possibly that logical AND function could be performed by the uC... the OD signal is routed to a uC pin and the OD MOSFET gate is controlled directly by another uC GPIO pin. The uC turns on the MOSFET only if the OD signal is high and it wants power on to the rest of the system.

[zenekNY]

My apologies, I misread your previous reply.
I think that the most feasible way will be to add a third N channel Mosfet like you suggested and leave the protection IC alone.

Ideally I would like to use a physical circuit which would force the entire system to power down in case something went wrong with the program but I find it difficult to integrate it, as I’m just a rookie

[zenekNY]

I like the idea of the uC reading state of the OD pin and controlling the gate on the mosfet, but in this case the uC wouldn’t be able to shut itself off when the battery would discharge to a critical level and would keep slowly draining the battery, where the purpose of the protection IC is to keep it from Over Discharging.

[Peabody]

I think Q1 is upside down.  It's a PNP, so the emitter should be connected to OD, and the collector to the mosfet gate.  And there needs to be a high-value pulldown resistor on the gate.

So PB4 goes high, which turns on Q3, which turns on Q1 (but only if OD is high), which passes the high from OD to the mosfet gate, and that turns on the power.  Isn't that what you want?  If you bring PB4 low, that turns off Q3, and R4 turns off Q1, and the gate pulldown turns off the power.

R5 may need to be a higher value depending on how much current OD sources.

I think normally the protection mosfet gates don't have pulldown resistors because OC and OD are always active - either high or low, but never floating.  But Q1 interrupts that because it can either source current to the gate, or not, but can't actively bring it low, and if you don't bring it low, it will stay high.  It's just a charged capacitor, basically.

Edit:  Make sure you connect to the right mosfet.  If you don't, power can flow through the mosfet body diode even if the mosfet is off.  What's shown in your schematic is correct.  Just make sure that's how you've connected it.

[Peabody]

I'm attaching a revised version of your circuit showing (in a red box) the changes I'm suggesting.  I've left off the pin numbers of the PNP because I don't know what part you're using.  And I'd suggest you check that carefully because the PNPs I use don't have the pinout you show.  Anyway, I think this ought to work.

[ Attachment Invalid Or Does Not Exist ]

[ledtester]

> but in this case the uC wouldn’t be able to shut itself off when the battery would discharge to a critical level

in sleep mode the uC only consumes microamps (perhaps even nanoamps) and can still respond to pin changes. This is far less than the self-discharge current of the battery itself.

[zenekNY]

I decided to add another Mosfet right after the dual channel one and not mess around with the protection IC, I want to be able to reset the uC without taking the case apart.
I will not be able to add a battery switch to the system as I am trying to make the device dust and splash proof because it will be used in a pretty rough environment.
The only thing is that I have to order some Fets and it will be a while until I get them and I will probably redo my test board.

> I think Q1 is upside down.

I have a little test board made up just for the power latching circuit and I have the Collector pin on PNP going to the Gate of the Mosfet so I'm pretty sure
the Q1 is connected right. But please correct me if I'm wrong, I have had it connected wrong some time ago because I didn't pay attention in KiCad.

> R5 may need to be a higher value depending on how much current OD sources.

I used a 5M ohm resistor at one point and the pulldown was still too strong for the collector pin to pull it back up, probably like you said, due to the OD sourcing too weak of a signal/current.

I attached an image of the little test board I made up, the dashed lines are jumpers on the other side of the board as it is a single sided board.

[Peabody]

> I think Q1 is upside down.

I have a little test board made up just for the power latching circuit and I have the Collector pin on PNP going to the Gate of the Mosfet so I'm pretty sure
the Q1 is connected right. But please correct me if I'm wrong, I have had it connected wrong some time ago because I didn't pay attention in KiCad.

> R5 may need to be a higher value depending on how much current OD sources.

I used a 5M ohm resistor at one point and the pulldown was still too strong for the collector pin to pull it back up, probably like you said, due to the OD sourcing too weak of a signal/current.

I was just going on what your schematic shows.  It has the emitter connected to the gate.  But  you show it as a BCE, and I think most PNPs in SOT23 are BEC.  What transistor are you using?

5M is going way too far.  With the 4.7K, how about measuring the voltage at the critical points when you want the power to be on, and off.  PB4, OD, the mosfet gate, either side of R5.

I also wonder about having the switch and the Q3 stuff going to -BAT instead of to ground.  If that's correct, and it looks like it is, then my 1M pulldown resistor should also go to -BAT, not ground.

Well, you've decided to go another way, but it would still be nice to get this working in case you need it again in the future.  I think it ought to work.

[zenekNY]

Well I can keep messing around with this for another week until I get new order of parts and if it proves to work then I will just have some spare fets for future projects.

The NPN transistor I am using is this one here:

https://media.digikey.com/pdf/Data%20Sheets/Diodes%20PDFs/MMBT3906.pdf

I understand that the 5M was too high, I just wanted to see if even with a high resistance would I get the same result and it was cutting the power off.

As far as power goes, everything works fine up until and including the base of PNP  transistor. I will double check myself when I get home after work, but I’m pretty sure.

The voltage that I was getting on the OD to BAT- was wonky though. I remember reading like a 0.5V or something in that neighborhood. I will double check that too. I should also mention that reading voltage between OD and BAT- turns the power off as well, which is weird, because a voltmeter should be very little to non intrusive when it comes to power draw.

The protection IC that I’m using is this one here:

https://datasheet.lcsc.com/szlcsc/1810101017_Fortune-Semicon-DW01-G_C14213.pdf

After looking at the Functional diagram in the data sheet in my opinion I should be getting either LOW/HIGH from OD and OC, it uses a set of comparators on the CS input line and respective LOW/HIGH should be spit out depending on the state of CS line. But it’s just my theory

Also I looked at the Absolute Maximum Ratings table where the “OD output pin voltage” is rated at GND -0.3V to VCC +0.3V
, wouldn’t those voltages not be able “saturate/close” the gate?

[ledtester]

The protection IC that I’m using is this one here: https://datasheet.lcsc.com/szlcsc/1810101017_Fortune-Semicon-DW01-G_C14213.pdf

There's more details starting on page 14 including timing diagrams of the signals.

Also I looked at the Absolute Maximum Ratings table where the “OD output pin voltage” is rated at GND -0.3V to VCC +0.3V, wouldn’t those voltages not be able “saturate/close” the gate?

That spec sounds like the range to prevent CMOS latch-up - i.e. don't let the voltage on that pin exceed that range.

[Peabody]

I think the output voltage of OC and OD is fine.  It should be essentially +BAT.  But the current could be the problem.  The datasheet says the entire operating current of the DW01 is 3uA, and even that comes in through a 100R resistor.  So the problem may be that the emitter-base current of the PNP, which is needed to turn on the transistor, is just overwhelming whatever the output capability of OD is.  But it's strange that just measuring the voltage on OD would mess things up.

Do you have a logic-level P-channel mosfet you could try in place of the PNP?   There would be no current drain on OD with that.

[Peabody]

I dug out my famous "18650 battery shield V3" which is a single cell charger and boost converter.  It uses the typical DW01 protection, and all of that is accessible on the board.  I measured both OC and OD with respect to -BAT with my meter, and got a solid 4.11V, and measuring it didn't interrupt the power.  So I wonder what's going on with your DW01.

[zenekNY]

> So the problem may be that the emitter-base current of the PNP

That’s what I thought, even sending it through a base of another transistor to amplify it might be another option but then I’d be piling up more components on that simple circuit.

I will replace the IC with a new one, maybe it got fried in the process when I was poking around.

[Peabody]

Assuming you have a good DW01, I think the attached circuit is what I would suggest.  It would replace the PNP transistor with a P-channel mosfet.  That would eliminate any current demands on OD except for the 4uA that the pulldown resistor would draw.  The  pulldown is connected to -BAT.

I think there is a wide variety of P-channel mosfets in SOT23 that have the same pinout as your 2N3906 PNP.  So it should be a drop-in replacement.  Something like the DMP1045U should wor

[zenekNY]

So here is what I did to make sure all components are in good condition:
- I desoldered a PNP transistor to clear OD pin on the DW01.
- I tested for voltage on OD pin and it read 3.8V with PNP removed, that lead me to believe there might be something wrong with the transistor,
- went ahead and  replaced the DW01 and the mosfet anyways to make sure the components that are giving me a hard time are in working order.
- Both OC and OD were putting out 3.8V without the transistor,
- I go to solder the PNP transistor on and put a 1M resistor on the PNP Collector/Gate line, the voltage reads 2.28V
 on the emmiter and the collector, 1.6V on the Base. It goes to a default ON (Not what I want).

I go to hold a button to tell the uC to pull a gate on NPN high, this results in a 1V on a PNP Collector/Gate line. 3.8V on Collector and 3.7V on base.
I also tried putting a 330K pulldown which too, gave me 1V on the PNP Collector/Gate line.

I'm not sure why would I be getting 1.6V on a base of the PNP transistor when the NPN should be forcing it to drop to 0V through a current limiting 4.7K resistor.

I'm attaching two images to show the voltages I am getting.

[zenekNY]

Assuming you have a good DW01, I think the attached circuit is what I would suggest.  It would replace the PNP transistor with a P-channel mosfet.  That would eliminate any current demands on OD except for the 4uA that the pulldown resistor would draw.  The  pulldown is connected to -BAT.

I think there is a wide variety of P-channel mosfets in SOT23 that have the same pinout as your 2N3906 PNP.  So it should be a drop-in replacement.  Something like the DMP1045U should work.

(Attachment Link)

this totally makes sense, I wish I didn't put in an order for components yesterday and grabbed a few P-Channel fets, but I will see if I could source a few on ebay or something.

[Peabody]

Make sure the 1M gate pulldown resistor goes to -BAT, not ground.  Then take all your meter measurements with respect to -BAT, not ground.  Do you get different numbers?

[zenekNY]

I should’ve mentioned that I did indeed measure everything to BAT-
The only place the GND (Drain) is used is the uC.