LDO output oscillation

[BobsURuncle]

You need filter capacitors near pin 2 (V+) of your reference chip to avoid instabilities in the output.

[technix]

You need filter capacitors near pin 2 (V+) of your reference chip to avoid instabilities in the output.

I have those (not shown in the schematics - see the board shot)

[technix]

Moved the op amp's power pin to the SMPS output to guarantee enough gate drive for the MOSFET. The SMPS output is solid as-is though. There is an oscillation about 100kHz at the output?

[Zero999]

So this happened. However I am still seeing some noise at about 100mV. The +12V rail comes from a boost converter so it is fairly noisy.

How do I fix the remaining gain problem without a significant C1? I need to reduce the noise.

Now you're getting somewhere. Try increasing the value of R7.

EDIT:

So here is the state of the circuit. Q1 should have unity gain, effectively a pure level shifter.

Trace on top = output, trace at bottom = input, both probes are x10.

Oh, sorry, missed that. You could even increase R7 further so it has a loss.

[T3sl4co1l]

Whyyy?? 

Why did you put additional gain, of uncertain magnitude, after the op-amp? 

A huge amount of it, no less.  Like 40dB excess!  It's guaranteed to oscillate that way.

I will tell you a secret. Gather 'round...

Checklist:
- Bounded inputs, bounded outputs (for all stages)
- Linear transfer function, bounds coincide on the curve
- Loop gain is in the stable range
- Phase shift doesn't blow out the op-amp's phase margin

You can tell gain is in the stable range, if the gain outside of the op-amp (in the loop from its output to its feedback input) is less than or equal to the reciprocal of its maximum stable gain.  (Which for most, is a gain of 1, i.e., "unity gain stable".  Some are "decompensated" and only stable at higher gains, or with compensation capacitors added to other pins.  The datasheet will tell.)

The above circuit fails because:

Bounded inputs
------------------
Op-amp inputs: has ESD protection diodes, and inputs are bounded voltage, or limited current (in the worst case, a limited current input will be clamped by the input protection diodes).  Good.
Gain stage (Q1): is driven by op-amp (bounded output).  Good.
Output stage (Q2): Unbounded.  Bad.

Bounded outputs
--------------------
Op-amp output: 0 to 5V.  Limited current capacity (10s of mA?).  Good.
Gain stage (Q1): 0 to +12V.  Not very good: greatly exceeds the input range of the following stage, and if +12V isn't limited elsewhere, neither will this be.  Unlimited current capacity: 100s of mA. 2N7000 is quite a beefy little MOSFET.  Bad.
Output stage: voltage is suitable for purpose (0 to +V).  Current: unlimited (10s of A?).  Bad.

Transfer functions
-------------------
Op-amp: only active in a narrow range (a diference of some mV), but that's okay, because we want all the loop gain centered here.  Good.
Gain stage (Q1): Nonlinear.  Offset (Vgs(th) not accounted for).  Saturates well before the full available range.  Uses maybe 1.0 to 1.5V out of a 0-5V range.  Exponential to quadratic curve, not linear (gain varies with quiescent point!).  Bad.
Output stage (Q2): Nonlinear.  Offset (Vgs(th) not accounted for).  Unlimited output current.  Turns on around -1V (relative to +V) and keeps going up from there, until 5-10V range where it's either saturated (Rds(on) resistive region -- in dropout) or at maximum amps, short circuit (10-30A?).  Gain varies proportional to load current.  Bad.

Loop gain
------------
Who knows?  The voltage gain from Q1 may be 10's, and the same for Q2.  In the threshold to subthreshold region, where both are just barely turning on, it might even be less than 1.

The wildly varying loop gain is a sure sign of having done something wrong.

Phase shift
------------
Again, who knows?  Q1 at least isn't driving much of a load.  Q2's gate won't be the tiniest thing ever, but it won't dominate the loop response.  It may be relevant towards the cutoff frequency though.

Q2 isn't driving a capacitive load, which is unusual, and probably not a good thing: having little load (especially at high frequency) means the loop gain is very high (especially at high frequencies).  So you're also in a bit of a worst-case situation, for the load shown.

Ideally, the phase shift across the transistors should be small (or, put another way, their frequency response as amplifiers should be higher than the op-amp's fT), which shouldn't be hard to arrange.


So, how to fix it?
--------------------

By now, you should be able to guess the most obvious help: reduce the gain of Q1 and Q2, so that they more fully utilize the voltage ranges available.

Simplest solution: add a source degeneration resistor to Q1.  This reduces the voltage gain and increases the input voltage range.  It doesn't remove the offset, but it makes it less important.  (Changing to a BJT like 2N3904 would reduce the offset a bit, and also reduce capacitance.)

The same can be done for Q2, but this worsens dropout at high currents.  But a conceptual restructuring is in order, for that one.

Suppose you have a nice big capacitor on the output (which is typical for most applications!).  Outside of the resistive range, Q2 is only ever a transconductance amplifier (output current dependent on gate voltage).  It would be nice to stabilize its gain, so it is linear, and so its output current can be bounded responsibly.

A current source into a capacitor makes a single pole filter.  If we close the loop around that, with the op-amp being a second pole, we get an easily-solved second order system, which can be optimized for step response quite easily.

The challenge, then, is making Q2 have a nice, flat, limited operating range, without compromising its resistance.

Backing up a level -- once you make a clean, linear current source block, all you need to do is level-shift the error amplifier's output to meet the input range of the current source, providing little or no gain in the process.  Simply match up the output and input bounds.

Or converting the error amp's output to a constant current sink, if your current-source block works out better as a current amplifier or mirror (current in --> current out).  Bounding the input of the current source necessarily gives you a fixed and accurate current limit, thus solving the problem of short-circuit protection, too!



Tim

[technix]

Whyyy?? 

Why did you put additional gain, of uncertain magnitude, after the op-amp? 

A huge amount of it, no less.  Like 40dB excess!  It's guaranteed to oscillate that way.

I will tell you a secret. Gather 'round...

Checklist:
- Bounded inputs, bounded outputs (for all stages)
- Linear transfer function, bounds coincide on the curve
- Loop gain is in the stable range
- Phase shift doesn't blow out the op-amp's phase margin

You can tell gain is in the stable range, if the gain outside of the op-amp (in the loop from its output to its feedback input) is less than or equal to the reciprocal of its maximum stable gain.  (Which for most, is a gain of 1, i.e., "unity gain stable".  Some are "decompensated" and only stable at higher gains, or with compensation capacitors added to other pins.  The datasheet will tell.)

The above circuit fails because:

Bounded inputs
------------------
Op-amp inputs: has ESD protection diodes, and inputs are bounded voltage, or limited current (in the worst case, a limited current input will be clamped by the input protection diodes).  Good.
Gain stage (Q1): is driven by op-amp (bounded output).  Good.
Output stage (Q2): Unbounded.  Bad.

Bounded outputs
--------------------
Op-amp output: 0 to 5V.  Limited current capacity (10s of mA?).  Good.
Gain stage (Q1): 0 to +12V.  Not very good: greatly exceeds the input range of the following stage, and if +12V isn't limited elsewhere, neither will this be.  Unlimited current capacity: 100s of mA. 2N7000 is quite a beefy little MOSFET.  Bad.
Output stage: voltage is suitable for purpose (0 to +V).  Current: unlimited (10s of A?).  Bad.

Transfer functions
-------------------
Op-amp: only active in a narrow range (a diference of some mV), but that's okay, because we want all the loop gain centered here.  Good.
Gain stage (Q1): Nonlinear.  Offset (Vgs(th) not accounted for).  Saturates well before the full available range.  Uses maybe 1.0 to 1.5V out of a 0-5V range.  Exponential to quadratic curve, not linear (gain varies with quiescent point!).  Bad.
Output stage (Q2): Nonlinear.  Offset (Vgs(th) not accounted for).  Unlimited output current.  Turns on around -1V (relative to +V) and keeps going up from there, until 5-10V range where it's either saturated (Rds(on) resistive region -- in dropout) or at maximum amps, short circuit (10-30A?).  Gain varies proportional to load current.  Bad.

Loop gain
------------
Who knows?  The voltage gain from Q1 may be 10's, and the same for Q2.  In the threshold to subthreshold region, where both are just barely turning on, it might even be less than 1.

The wildly varying loop gain is a sure sign of having done something wrong.

Phase shift
------------
Again, who knows?  Q1 at least isn't driving much of a load.  Q2's gate won't be the tiniest thing ever, but it won't dominate the loop response.  It may be relevant towards the cutoff frequency though.

Q2 isn't driving a capacitive load, which is unusual, and probably not a good thing: having little load (especially at high frequency) means the loop gain is very high (especially at high frequencies).  So you're also in a bit of a worst-case situation, for the load shown.

Ideally, the phase shift across the transistors should be small (or, put another way, their frequency response as amplifiers should be higher than the op-amp's fT), which shouldn't be hard to arrange.


So, how to fix it?
--------------------

By now, you should be able to guess the most obvious help: reduce the gain of Q1 and Q2, so that they more fully utilize the voltage ranges available.

Simplest solution: add a source degeneration resistor to Q1.  This reduces the voltage gain and increases the input voltage range.  It doesn't remove the offset, but it makes it less important.  (Changing to a BJT like 2N3904 would reduce the offset a bit, and also reduce capacitance.)

The same can be done for Q2, but this worsens dropout at high currents.  But a conceptual restructuring is in order, for that one.

Suppose you have a nice big capacitor on the output (which is typical for most applications!).  Outside of the resistive range, Q2 is only ever a transconductance amplifier (output current dependent on gate voltage).  It would be nice to stabilize its gain, so it is linear, and so its output current can be bounded responsibly.

A current source into a capacitor makes a single pole filter.  If we close the loop around that, with the op-amp being a second pole, we get an easily-solved second order system, which can be optimized for step response quite easily.

The challenge, then, is making Q2 have a nice, flat, limited operating range, without compromising its resistance.

Backing up a level -- once you make a clean, linear current source block, all you need to do is level-shift the error amplifier's output to meet the input range of the current source, providing little or no gain in the process.  Simply match up the output and input bounds.

Or converting the error amp's output to a constant current sink, if your current-source block works out better as a current amplifier or mirror (current in --> current out).  Bounding the input of the current source necessarily gives you a fixed and accurate current limit, thus solving the problem of short-circuit protection, too!



Tim

I actually have NPN current mirror chip (BCV61) so how to do that? OPA to 510 ohm or 4.7k into the input leg of BCV61, 510 ohm discharge resistor into the other leg of BCV61?

[technix]

So this happened. However I am still seeing some noise at about 100mV. The +12V rail comes from a boost converter so it is fairly noisy.

How do I fix the remaining gain problem without a significant C1? I need to reduce the noise.

Now you're getting somewhere. Try increasing the value of R7.

EDIT:

So here is the state of the circuit. Q1 should have unity gain, effectively a pure level shifter.

Trace on top = output, trace at bottom = input, both probes are x10.

Oh, sorry, missed that. You could even increase R7 further so it has a loss.

Like this?

[Zero999]

So this happened. However I am still seeing some noise at about 100mV. The +12V rail comes from a boost converter so it is fairly noisy.

How do I fix the remaining gain problem without a significant C1? I need to reduce the noise.

Now you're getting somewhere. Try increasing the value of R7.

EDIT:

So here is the state of the circuit. Q1 should have unity gain, effectively a pure level shifter.

Trace on top = output, trace at bottom = input, both probes are x10.

Oh, sorry, missed that. You could even increase R7 further so it has a loss.

Like this?

I wouldn't go that far, as the MOSFET may not have a high enough gate voltage to turn on.

Does it have to be a MOSFET? Can't you use a BJT? It would be much easier to stabilise?

[technix]

So this happened. However I am still seeing some noise at about 100mV. The +12V rail comes from a boost converter so it is fairly noisy.

How do I fix the remaining gain problem without a significant C1? I need to reduce the noise.

Now you're getting somewhere. Try increasing the value of R7.

EDIT:

So here is the state of the circuit. Q1 should have unity gain, effectively a pure level shifter.

Trace on top = output, trace at bottom = input, both probes are x10.

Oh, sorry, missed that. You could even increase R7 further so it has a loss.

Like this?

I wouldn't go that far, as the MOSFET may not have a high enough gate voltage to turn on.

Does it have to be a MOSFET? Can't you use a BJT? It would be much easier to stabilise?

The output stage must be a MOSFET as I am shooting for an extremely low (sub-volt) drop-out voltage. This is used in my high efficiency lab power supply project, which uses an adjustable linear LDO power supply and a tracking SMPS to minimize both noise and loss.

I could have gone with a pure SMPS design, but low-ripple SMPS gets very complicated at high power levels. (15V 50mA with 10mVpp ripple is easily achievable even with MC34063, but 15V 3A with 10mVpp ripple is a whole another story.)

[T3sl4co1l]

Mind that:
1. LDO is a terrible architecture to begin with, for low ripple applications.  Remember all that stuff about loop gain and frequency response?  The loop gain is also your ripple reduction (factored by Q2's Coss).  It gets worse as you go up in frequency!
2. Since you have a higher supply voltage available, you can use a conventional follower topology with no penalty.  Which means high performance BJTs are on the table!
3. If you need low ripple, you probably don't need high efficiency.  Why not skip the pre-regulator entirely?
4. If you need low ripple, you probably don't need an incredibly precise voltage.  Why not use a capacitor multiplier, or several?
5. If you do need both, why not use a C-mult. and wrap the feedback loop around that?  (You don't even need a post-regulator, you can simply servo the SMPS to it.  Slowly, but good enough.)

Tim

[technix]

Mind that:
1. LDO is a terrible architecture to begin with, for low ripple applications.  Remember all that stuff about loop gain and frequency response?  The loop gain is also your ripple reduction (factored by Q2's Coss).  It gets worse as you go up in frequency!
2. Since you have a higher supply voltage available, you can use a conventional follower topology with no penalty.  Which means high performance BJTs are on the table!
3. If you need low ripple, you probably don't need high efficiency.  Why not skip the pre-regulator entirely?
4. If you need low ripple, you probably don't need an incredibly precise voltage.  Why not use a capacitor multiplier, or several?
5. If you do need both, why not use a C-mult. and wrap the feedback loop around that?  (You don't even need a post-regulator, you can simply servo the SMPS to it.  Slowly, but good enough.)

Tim

I can try running with a source follower N-channel MOSFET, but regardless the power component must be a MOSFET, as I really don't want to tackle the base current of the power BJT.

The project I am designing have a 17V input rail (unregulated from the transformer,) the two-phase tracking synchronous buck converter output (so I can get more current than the transformer can supply when the output voltage is low) and the main output. (there is, of course, also a separate 5V rail used by op amps, ADC and the microcontroller) I can use a low Vgs(th) MOSFET here.

[Audioguru]

Most opamps oscillate if there is a capacitor to ground on the output like you have. The datasheet for the TLC2272 opamp you have shows pretty poor stability if the capacitor to ground on the output is 100pF or more and show that if you need a capacitor then isolate it from the output of the opamp with a 100 ohm series resistor.

Most LDO regulators need a mandatory capacitor to ground on their output, because the series pass device has gain (most ordinary regulators have an emitter follower or source follower with no gain).

[T3sl4co1l]

Most opamps oscillate if there is a capacitor to ground on the output like you have. The datasheet for the TLC2272 opamp you have shows pretty poor stability if the capacitor to ground on the output is 100pF or more and show that if you need a capacitor then isolate it from the output of the opamp with a 100 ohm series resistor.

Most LDO regulators need a mandatory capacitor to ground on their output, because the series pass device has gain (most ordinary regulators have an emitter follower or source follower with no gain).

Look carefully; the cap's not going to ground. 

Tim

[David Hess]

Most opamps oscillate if there is a capacitor to ground on the output like you have. The datasheet for the TLC2272 opamp you have shows pretty poor stability if the capacitor to ground on the output is 100pF or more and show that if you need a capacitor then isolate it from the output of the opamp with a 100 ohm series resistor.

Unless there is a schematic that I missed, that 330pF capacitor is between the output and inverting input and rolls off the frequency response starting at 64kHz.

Most LDO regulators need a mandatory capacitor to ground on their output, because the series pass device has gain (most ordinary regulators have an emitter follower or source follower with no gain).

I agree; the output capacitance needs to be included in the design.

technix, I think you are going about this the wrong way which will only lead to tears.  A low dropout common source or emitter design will require a lot more effort to reject high frequency ripple then a source or emitter follower design.  If you must do this, then add an LCR filter at the input and definitely include the output capacitor which is required for good LDO performance anyway.  Using a breadboard for prototyping is not ideal but you can probably get away with that since a better construction method will improve performance.

I have done what you are trying in the past with both standard and low dropout designs and besides using careful filtering at the input and attention to ground loops, I included a separate high frequency discrete feedback loop (effectively T3sl4co1l's capacitance multiplier suggestion but I never thought of it that way) at the pass transistor from the low frequency control loop using the operational amplifier.

[xavier60]

The ripple regulation might improve if the opamp is allowed to have more high frequency or proportional gain by putting a resistor in series with C1.

[Zero999]

Try this but it will oscillate with a low ESR output capacitor. The transient response also isn't great. The load is a 1R resistor which is switched on and off to test the transient response.

[T3sl4co1l]

Y'know, an R || L would probably help, in series with the drain, just after the feedback is tapped off.  ESR serves the same purpose, but this stabilizes it at high frequency, regardless of load, so that gain and feedback stage keeps on working until its own roll-off frequency.

The local feedback to a ground referenced stage is good news for ripple rejection, at least until higher frequencies.

The gate driver is pretty poor.  It'll work for large swings, but that deadband is icky.    You could make a properly biased complementary emitter follower, at some expense to quiescent current and added parts.

PNP pass device is still an option, probably easier to drive because of the higher gain (dIc / dVbe).  DC base current isn't a big deal as long as hFE >= 100, which is easy enough to find.  Base current requirement doubles as an excuse for quiescent current, so you don't need a crazy driver.

Tim

[technix]

Maybe I should just try to improve on the SMPS design to achieve low output ripple then? Currently the two-phase design is based on LM2642, but maybe I can try build my own using STM32? (also using a multi-phase synchronize rectifying design, but since I am using a MPU I can turn phases on and off as needed)

[T3sl4co1l]

What's wrong with tacking on extra filtering?  Is the LM2642 known to produce subharmonic ripple or something?

A 5th order lowpass at 50kHz should do a fine job of filtering ~300kHz ripple.  Put a 3rd order on the input also, and use common mode chokes and shielding as necessary.  Quiet as can be!

Tim

[technix]

What's wrong with tacking on extra filtering?  Is the LM2642 known to produce subharmonic ripple or something?

A 5th order lowpass at 50kHz should do a fine job of filtering ~300kHz ripple.  Put a 3rd order on the input also, and use common mode chokes and shielding as necessary.  Quiet as can be!

Tim

LM2642 cannot output arbitrarily low voltage, and requires external compensation as it too uses an analog control loop. For the STM32-based design the MCU's limited ADC speed naturally rolls off the response frequency to a few tens of kHz at best, the entire compensation circuit can be replaced with a software compensation algorithm, it can go for as low as the ADC allows it to for the output, and it can be controlled using isolated UART (or UART over optical fiber.)

[T3sl4co1l]

I don't see why not.  What in the LM2642 limits output voltage?

If you mean because the voltage sense is fixed at 1.3V, you are using way less imagination than it takes to make a better system with DSP.

Tim

[snarkysparky]

I would try putting a resistor voltage divider between the  op amp output and the gate of Q1.
The divider will apply the lowest voltage to the gate  that solidly turns on Q1 with the op amp output at maximum voltage.

Another divider between the drain of Q1 and the gate of Q2 such that with Q1 fully switched on the gate of Q2 is pulled just low enough to fully turn on Q2.

This helps reduce unnecessary gain.

[technix]

I don't see why not.  What in the LM2642 limits output voltage?

If you mean because the voltage sense is fixed at 1.3V, you are using way less imagination than it takes to make a better system with DSP.

Tim

When the output voltage of LM2642 is changed, the entire component value calculation is thrown off and way too many components have to be recalculated,, especially when the differences of the output voltages are vast. For STM32-based SMPS, the same compensation algorithm can still work.

[T3sl4co1l]

Well gee, if you're dependent on their calculation tool, sure, but why would you voluntarily excuse yourself from using your own brain?

If you use the simulation model instead (I assume the thing is in Tina-TI or whatever), you can probably find a combination of parts, and a circuit, that works.  That model might not even be made to accommodate such operation.  You might have to breadboard the poor thing to truly find out!

Tim

[technix]

Well gee, if you're dependent on their calculation tool, sure, but why would you voluntarily excuse yourself from using your own brain?

If you use the simulation model instead (I assume the thing is in Tina-TI or whatever), you can probably find a combination of parts, and a circuit, that works.  That model might not even be made to accommodate such operation.  You might have to breadboard the poor thing to truly find out!

Tim

Even with that in mind I still need DACs and digipots to control it don't I?

If a MCU-based solution is used, by using logic-level MOSFETs, there is absolutely zero interfacing circuitry required.