Author Topic: Loading effect of a transmission line  (Read 1738 times)

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Offline Mark IVTopic starter

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Loading effect of a transmission line
« on: October 08, 2018, 05:04:32 pm »
Hi all!

I'm trying to understand some stuff about high speed logic and transmission lines...In particular, i'm trying to figure out how a transmission line affects the rise time of a signal.

For example, assuming I have a LVCMOS driver (quite fast) with a source termination resistor to match 50ohm, a PCB trace long enough to consider it a TL (Z0 = 50 ohm, of course) and a LVCMOS receiver with 5 pF of input capacitance. How is going to be the rise time at the receiver? It depends only in the load? Is it somehow predictable (for example, what happens if I attach another receiver to the line at the same point) Is the capacitance trace ( https://www.edn.com/design/pc-board/4427201/Rule-of-Thumb--5--Capacitance-per-length-of-50-Ohm-transmission-lines-in-FR4 ) and therefore the length of the transmission line a factor to consider?
 

:-//
 

Offline Benta

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Re: Loading effect of a transmission line
« Reply #1 on: October 08, 2018, 05:57:18 pm »
An ideal 50 ohms transmission line when terminated correctly (meaning receiver AND transmitter have 50-ohm impedance) should not influence rise and fall time. It does introduce delay, though.

Now in your case, you have additional capacitive loading at the receiving end, which will influence your signal integrity. There are ways to get around this, for example through a complex conjugate impedance at the transmitting end.

« Last Edit: October 08, 2018, 07:27:42 pm by Benta »
 

Offline _Wim_

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Re: Loading effect of a transmission line
« Reply #2 on: October 08, 2018, 06:29:47 pm »
This Tektronix video was posted here somewhere in the last weeks (forgot where and by who), but it explains transmission lines really wel:



 

Offline T3sl4co1l

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Re: Loading effect of a transmission line
« Reply #3 on: October 08, 2018, 08:50:21 pm »
For the circuit as described, the rise time is: "depends on line length and PCB loss".

If ideal materials are used, then it's the same as at the source, minus the meager 5pF || 50 ohm = 250ps time constant.

LVC isn't quite that fast, so we can ignore higher order structure.

In reality, 5pF is part pin and bondwire capacitance, which have inductance -- they are themselves transmission lines.  Only once the signal enters the die itself, is it more of an RC transmission line regime.  A QFN can have pin bandwidth to 5GHz or more!

Also, assuming ground impedance is zero, which isn't the case, but a ground plane, and supplies bypassed to it at the supply pin(s), and ground vias very close to the pins, will do an okay job at that.

Oh, also, it depends on the TL type: microstrip is dispersive (even without a lossy substrate -- the wave travelling in air gets there first), whereas stripline is not.

PCI-e drivers for example are designed to deliver overshoot (spiky edges), so the receiver gets a sharper waveform despite everything.

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Online David Hess

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Re: Loading effect of a transmission line
« Reply #4 on: October 09, 2018, 03:46:36 pm »
I'm trying to understand some stuff about high speed logic and transmission lines...In particular, i'm trying to figure out how a transmission line affects the rise time of a signal.

If the transmission line is terminated, then it has practically no effect.  If the transmission line is not terminated, then reflections between the ends effectively retard the rise time.  If the source impedance is high and no load termination is used, then the transmission line looks capacitive and acts as a low pass filter producing a lower rise time.

Quote
For example, assuming I have a LVCMOS driver (quite fast) with a source termination resistor to match 50ohm, a PCB trace long enough to consider it a TL (Z0 = 50 ohm, of course) and a LVCMOS receiver with 5 pF of input capacitance. How is going to be the rise time at the receiver? It depends only in the load? Is it somehow predictable (for example, what happens if I attach another receiver to the line at the same point)

T3sl4co1l covered it.  The transmission line looks resistive and 50 ohms driving 5 picofarads produces an insignificant 250 picosecond time constant.  In this specific case, source termination means the incident wave is half the drive voltage and when it hits the open termination, it doubles producing the original voltage which reflects back to the source and is absorbed.  A receiver located at the midpoint of the transmission line will see *two* steps which may be a problem.

http://web.cecs.pdx.edu/~greenwd/xmsnLine_notes.pdf

Quote
Is the capacitance trace ( https://www.edn.com/design/pc-board/4427201/Rule-of-Thumb--5--Capacitance-per-length-of-50-Ohm-transmission-lines-in-FR4 ) and therefore the length of the transmission line a factor to consider?

The trace capacitance matters if the transmission line is not terminated.  If the transmission line is terminated, then it just looks resistive.
 


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