Author Topic: Logic analyser query  (Read 1655 times)

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Offline netdudeuk

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Logic analyser query
« on: March 01, 2015, 07:20:32 pm »
Hi

I've got my basic 6502 system running but as I don't have any I/O, I've just been confirming that code is being run by capturing D0 to D7, triggered on a D0 edge.  The code runs a very simple loop.  The address decoding outputs look as good as they can do with a logic probe and capturing the data bus mostly looks ok.  The stream of data looks pretty good and mostly follows the hex code from the ROM.  However, there are odd glitches where there's an extra high bit in a byte, quickly followed by the correct byte.  The specific bit varies.  I'm speculating that this is because unlike the system itself where control lines are used to signal valid data on the bus, I'm just grabbing the data as fast as I can and the buffered data lines may not all be quite ready at the sample points.  Does this sound reasonable ?

The CPU clock is 3MHz and I've been sampling up to 24MHz.

I think that if things were actually running bad inside the system, the code (and sampled data) would be all over the place but the loop itself is maintained.

Thanks

« Last Edit: March 03, 2015, 08:19:09 pm by netdudeuk »
 

Offline SeanB

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Re: Logic analyser query
« Reply #1 on: March 01, 2015, 08:40:02 pm »
That would be sampling errors. Change the trigger edge to whatever the 6502 uses and it will be stable.
 

Offline netdudeuk

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Re: Logic analyser query
« Reply #2 on: March 01, 2015, 08:54:32 pm »
Thanks Sean.  I think that you've probably confirmed my theory.

As I've only got eight channels in the analyser, I'm having to to trigger on one of those bits.  So, it's a rise on D0. Not perfect but probably good enough for me to know that I can add the next stage, which is the proper I/O.

 

Offline DJohn

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Re: Logic analyser query
« Reply #3 on: March 03, 2015, 01:34:36 pm »
The data lines won't all change at exactly the same time, so yes, that's your problem.

It might be better to look at half of the data bus at a time.  Keep one channel on the clock, one on a signal that will indicate the start of your loop (when I'm bringing up a 6502, I put the start of the loop at an address ending in 1ff, and don't access anything else at an address with bit 8 high.  Then I can use the falling edge of A8 as a loop trigger).  Capture D0-D3, then D4-D7 in another pass.  That leaves a couple of channels for part of the address, or R/W.

It's possible to do this with a 2 channel scope with external trigger and a bit of patience.
 

Online Howardlong

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Re: Logic analyser query
« Reply #4 on: March 03, 2015, 02:57:09 pm »
Back in the 70s, on the odd occasion we had access to a scope, we probed one bit at a time with a piece of paper and a pen. Painful, but we learned how to speak binary!

 


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