Logic Analyzers real freq. and measured freq.

[Yaro]

Hi all,

I've a question about logic analyzers and sample frequencies.

For example:

I've a logic analyzer that have a sample rate of 200Mhz.
I've a 20 Mhz clock(50% duty cycle) to sample and I've measured 16Mhz clock and sometimes 20Mhz clock when I sample this signal.

In the case I've a 50Mhz(50% duty cycle) clock to sample and a 100Mhz(50% duty cycle) clock to sample, I've measured respectively a 10/11Mhz clock and 15/20Mhz clock. In which of this two case I loose data(can't sample a logic 1 state for example) and how I can determinate relationship between sample clock, signal clock to sample and clock I get?

[pcblearner]

Can you check on an oscilloscope to see if you actually are getting 20/50/100MHz from the clocks?
It sounds like perhaps the logic analyzer is not configured for your circuit; I would double check the signal HI/LO levels you are using match what the analyzer expects, and also check if there is a prescaler enabled that could be dividing the clock input.

[suicidaleggroll]

What logic analyzer are you using?

[free_electron]

could be, as there is no phase relation between your clock and the sampling point of the LA.
you will need to set up the analyser to trigger from this clock and then run the analyzer. so if the frequencies perfectly align you should get 5 samples high and 5 samples low a 20MHz clock sampled at 200MHz gives you a max of 10 samples.

if there is the slightest phase shift or the clock is off ( 19.9999 MHz )  you will get 5 samples high and 6 samples low. in this case the analyzer will give you 1/5 error. 1.5 of 20 is 4MHz .. so it will tel you 16 MHz ... if oyu feed it 20.000001 it will tell you 20 MHz.

Sampling a 50Mhz clock at 200 MHz hives you 4 samples. be 1 sample off and you drop 1/4