There are lots of ways to do this. I'm assuming you want something simple.
Here's how we'd have done it back in "the old days" of SSI.
I'm assuming that you want to decode 16 bits to see if they match exactly one address.
This block of logic has two inputs IN<15:0> (16 bits)
and ADDR<15:0> (the address we're matching against)
Option 1. Compare each bit of IN to the corresponding bit in ADDR. You do this with an
XOR gate. Then check to make sure the output of every XOR gate is false.
That takes 16 XOR gates (like four 7486 chips), 2 8-input NAND gates (2 x 7430) and one 2 input NOR (1/4 * 7402)
Option 2. Build it out of muxes -- this is also known as a poor man's PLA.
It will take four 16:1 muxes (like a 74HC4067 or 74150). we'll call them U1,U2,U3,U4
U1 select inputs are connected to IN<3:0>
U2 """"" to IN<7:4>
U3 to IN<11:8>
U4 to IN<15:12>
Now this is where it gets a little complicated.
Tie all the data inputs (E0...E15 in the drawing I found at
http://ee-classes.usc.edu/ee459/library/datasheets/sn74150.pdfhigh by default. But one of them on each chip will be tied low.
On U1, tie the Ex input low that corresponds to the value of ADDR<3:0> That is if ADDR<3:0> is 0b1010, tie E10 low.
On U2 tie the bit corresponding to ADDR<7:4>
U3 .. Addr<11:8>
U4 .. Addr<15:12>
All of the 16:1 muxes need to have their ENABLE pins tied low.
Now connect all the W outputs to the input of a 4 input NAND. (7420)
The output of this NAND gate will be LOW when the address matches.
I'm sure you can imagine other ways of doing this with 8:1 muxes or even
decoders and muxes. These are the two obvious ways, assuming 1980's
technology.
I can't imagine using an FPGA for this (and I spent 20+ years as a chip designer).
If this is the only function you need, there are probably a bunch of PLA or
PLDs that can do it. Your initial notion of a ROM would work too.
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